Heterogeneous defect prediction (HDP) is to detect the largest number of defective software modules in one project by using historical data collected from other projects with different metrics. However, these data can not be directly used because of different metrics set among projects. Meanwhile, software data have more non-defective instances than defective instances which may cause a significant bias towards defective instances. To completely solve these two restrictions, we propose unsupervised deep domain adaptation approach to build a HDP model. Specifically, we firstly map the data of source and target projects into a unified metric representation (UMR). Then, we design a simple neural network (SNN) model to deal with the heterogeneous and class-imbalanced problems in software defect prediction (SDP). In particular, our model introduces the Maximum Mean Discrepancy (MMD) as the distance between the source and target data to reduce the distribution mismatch, and use the cross-entropy loss function as the classification loss. Extensive experiments on 18 public projects from four datasets indicate that the proposed approach can build an effective prediction model for heterogeneous defect prediction (HDP) and outperforms the related competing approaches.

In this paper, a novel eight-way Ka-band spatial power combining structure based on SIW/HMSIW is presented and studied. The power-combining structure is realized by transitions between HMSIW and parallel multiport planar microstrip lines. The power combiner is designed and fabricated in 33.5-35 GHz. The measured results show a good agreement with simulation and a combining efficiency of 72% is achieved at 34.3 GHz.

Traditional low-rank feature lose the temporal information among action sequence. To obtain the temporal information, we split an action video into multiple action subsequences and concatenate all the low-rank features of subsequences according to their time order. Then we recognize actions by learning a novel dictionary model from concatenated low-rank features. However, traditional dictionary learning models usually neglect the similarity among the coding coefficients and have bad performance in dealing with non-linearly separable data. To overcome these shortcomings, we present a novel similarity constrained discriminative kernel dictionary learning for action recognition. The effectiveness of the proposed method is verified on three benchmarks, and the experimental results show the promising results of our method for action recognition.

In this paper, we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing Processor Array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications. As an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LSI. Design formulas for Window-MSPA architecture are given for various size of window operations in image processing. Thus, the derived architecture is flexible enough to satisfy user's requirement for either area or speed.

In this paper, a new bits truncation adaptive pyramid (BTAP) algorithm for motion estimation is presented. The method employs bits truncation of the gray level from 8bits to much less bits in the searching algorithm. Compared with conventional fast block matching algorithms, this method drastically improves speed for motion estimation of reduced gray-level images and preserves reasonable performance and algorithm reliability. Bits truncation concept is well combined with hierarchical pyramid algorithm in order to truncate adaptively according to image characteristics. The computation complexity is much less than that of pyramid algorithm and 3-Step motion estimation algorithm because of bit-truncated searbh and low overhead adaptation. Nevertheless, the PSNR property is also comparable with these two algorithms for various video sequences.

In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.

Massive multiple-input multiple-output (MIMO) is an enabling technology for next-generation wireless systems because it provides significant improvements in data rates compared to existing small-scale MIMO systems. However, the increased number of antennas results in high computational complexity for data detection, and requires more efficient detection algorithms. In this paper, we propose a new data detector based on a box-constrained complex-valued dichotomous coordinate descent (BCC-DCD) algorithm for large-scale MIMO systems. The proposed detector involves two steps. First, a transmitted data vector is detected using the BCC-DCD algorithm with a large number of iterations and high solution precision. Second, an improved soft output is generated by reapplying the BCC-DCD algorithm, but with a considerably smaller number of iterations and 1-bit solution precision. Numerical results demonstrate that the proposed method outperforms existing advanced detectors while possessing lower complexity. Specifically, the proposed method provides significantly better detection performance than a BCC-DCD algorithm with similar complexity. The performance advantage increases as the signal-to-noise ratio and the system size increase.

In this letter, a broadband coupler is presented that makes use of a half mode substrate integrated waveguide (HMSIW) technique using a printed circuit board process. The coupler is realized by a parallel HMSIW line which couples energy by magnetic field. Compared with micro-strip coupler and conventional HMSIW coupler, it has lower loss and better Electromagnetic Compatibility owning to the closed field structure. Compared with SIW coupler, it has smaller size and lower cost owing to the half TE10 model. The coupler is simulated and measured at 8-12 GHz. Measured results show a good agreement with simulation.

We have developed a low-power, high-performance MPEG-4 codec LSI for mobile video applications. This codec LSI is capable of up to CIF 30-fps encoding, making it suitable for various visual applications. The measured power consumption of the codec core was 9 mW for QCIF 15-fps codec operation and 38 mW for CIF 30-fps encoding. To provide an error-robust MPEG-4 codec, we implemented an error-resilience function in the LSI. We describe the techniques that have enabled low power consumption and high performance and discuss our test results.