Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits

Kazuteru NAMBA; Hideo ITO

doi:10.1587/transfun.E92.A.2295

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits

Kazuteru NAMBA, Hideo ITO

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The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.9 pp.2295-2303

Publication Date: 2009/09/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E92.A.2295

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Kazuteru NAMBA, Hideo ITO, "Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits" in IEICE TRANSACTIONS on Fundamentals, vol. E92-A, no. 9, pp. 2295-2303, September 2009, doi: 10.1587/transfun.E92.A.2295.
Abstract: The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2295/_p

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@ARTICLE{e92-a_9_2295,
author={Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits},
year={2009},
volume={E92-A},
number={9},
pages={2295-2303},
abstract={The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.},
keywords={},
doi={10.1587/transfun.E92.A.2295},
ISSN={1745-1337},
month={September},}

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TY - JOUR
TI - Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2295
EP - 2303
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transfun.E92.A.2295
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2009
AB - The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
ER -