IEICE TRANSACTIONS on Electronics
1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver
Summary :
A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.6 pp.835-842
- Publication Date
- 2009/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.835
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
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Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, "1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 835-842, June 2009, doi: 10.1587/transele.E92.C.835.
Abstract: A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.835/_p
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@ARTICLE{e92-c_6_835,
author={Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver},
year={2009},
volume={E92-C},
number={6},
pages={835-842},
abstract={A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.},
keywords={},
doi={10.1587/transele.E92.C.835},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - 1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver
T2 - IEICE TRANSACTIONS on Electronics
SP - 835
EP - 842
AU - Tatsuo NAKAGAWA
AU - Tatsuji MATSUURA
AU - Eiki IMAIZUMI
AU - Junya KUDOH
AU - Goichi ONO
AU - Masayuki MIYAZAKI
PY - 2009
DO - 10.1587/transele.E92.C.835
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
ER -
English
