Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
Summary :
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.4 pp.475-482
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.475
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
- Category
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Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, "Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 475-482, April 2009, doi: 10.1587/transele.E92.C.475.
Abstract: Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.475/_p
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@ARTICLE{e92-c_4_475,
author={Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations},
year={2009},
volume={E92-C},
number={4},
pages={475-482},
abstract={Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.},
keywords={},
doi={10.1587/transele.E92.C.475},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
T2 - IEICE TRANSACTIONS on Electronics
SP - 475
EP - 482
AU - Mitsuya FUKAZAWA
AU - Masanori KURIMOTO
AU - Rei AKIYAMA
AU - Hidehiro TAKATA
AU - Makoto NAGATA
PY - 2009
DO - 10.1587/transele.E92.C.475
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
ER -
English
