A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
Summary :
The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.5 pp.671-675
- Publication Date
- 2009/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.671
- Type of Manuscript
- Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jae-Young PARK, Jong-Kyu SONG, Chang-Soo JANG, San-Hong KIM, Won-Young JUNG, Taek-Soo KIM, "A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 5, pp. 671-675, May 2009, doi: 10.1587/transele.E92.C.671.
Abstract: The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.671/_p
Copy
@ARTICLE{e92-c_5_671,
author={Jae-Young PARK, Jong-Kyu SONG, Chang-Soo JANG, San-Hong KIM, Won-Young JUNG, Taek-Soo KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits},
year={2009},
volume={E92-C},
number={5},
pages={671-675},
abstract={The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.},
keywords={},
doi={10.1587/transele.E92.C.671},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 671
EP - 675
AU - Jae-Young PARK
AU - Jong-Kyu SONG
AU - Chang-Soo JANG
AU - San-Hong KIM
AU - Won-Young JUNG
AU - Taek-Soo KIM
PY - 2009
DO - 10.1587/transele.E92.C.671
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
ER -
English
