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[Author] Sun Young HWANG(2hit)

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  • Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching

    Woo Joo KIM  Sung Hee LEE  Sun Young HWANG  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E92-A No:3
      Page(s):
    890-899

    This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia data in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 444 mesh-type NoC architecture based on circuit switching, which is capable of processing GT signals requiring high throughput. The proposed NoC architecture shows reduction in area by 50.2% and in power consumption by 57.4% compared with the conventional NoC architecture based on circuit switching. These figures amount to by 72.4% and by 86.1%, when compared with an NoC architecture based on packet switching. The proposed NoC architecture operates in the maximum throughput of 19.2 Gb/s.

  • Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology

    Woo Joo KIM  Sun Young HWANG  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E91-A No:11
      Page(s):
    3297-3303

    This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.