IEICE TRANSACTIONS on Fundamentals
Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology
Summary :
This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.11 pp.3297-3303
- Publication Date
- 2008/11/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.11.3297
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Woo Joo KIM, Sun Young HWANG, "Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 11, pp. 3297-3303, November 2008, doi: 10.1093/ietfec/e91-a.11.3297.
Abstract: This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.11.3297/_p
Copy
@ARTICLE{e91-a_11_3297,
author={Woo Joo KIM, Sun Young HWANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology},
year={2008},
volume={E91-A},
number={11},
pages={3297-3303},
abstract={This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.},
keywords={},
doi={10.1093/ietfec/e91-a.11.3297},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3297
EP - 3303
AU - Woo Joo KIM
AU - Sun Young HWANG
PY - 2008
DO - 10.1093/ietfec/e91-a.11.3297
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2008
AB - This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.
ER -
English
