A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique

Xian Ping FAN; Pak Kwong CHAN; Piew Yoong CHEE

doi:10.1587/transele.E92.C.719

A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique

Xian Ping FAN, Pak Kwong CHAN, Piew Yoong CHEE

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A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm², consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E92-C No.5 pp.719-727

Publication Date: 2009/05/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E92.C.719

Type of Manuscript: PAPER

Category: Electronic Circuits

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Xian Ping FAN, Pak Kwong CHAN, Piew Yoong CHEE, "A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique" in IEICE TRANSACTIONS on Electronics, vol. E92-C, no. 5, pp. 719-727, May 2009, doi: 10.1587/transele.E92.C.719.
Abstract: A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm², consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.719/_p

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@ARTICLE{e92-c_5_719,
author={Xian Ping FAN, Pak Kwong CHAN, Piew Yoong CHEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique},
year={2009},
volume={E92-C},
number={5},
pages={719-727},
abstract={A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm², consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.},
keywords={},
doi={10.1587/transele.E92.C.719},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 719
EP - 727
AU - Xian Ping FAN
AU - Pak Kwong CHAN
AU - Piew Yoong CHEE
PY - 2009
DO - 10.1587/transele.E92.C.719
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm², consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.
ER -