IEICE TRANSACTIONS on Electronics
Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays
Summary :
This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 µm standard CMOS process for a 150
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.7 pp.1212-1219
- Publication Date
- 2011/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1212
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Chul Bum KIM, Doo Hyung WOO, Byung Hyuk KIM, Hee Chul LEE, "Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 7, pp. 1212-1219, July 2011, doi: 10.1587/transele.E94.C.1212.
Abstract: This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 µm standard CMOS process for a 150
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1212/_p
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@ARTICLE{e94-c_7_1212,
author={Chul Bum KIM, Doo Hyung WOO, Byung Hyuk KIM, Hee Chul LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays},
year={2011},
volume={E94-C},
number={7},
pages={1212-1219},
abstract={This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 µm standard CMOS process for a 150
keywords={},
doi={10.1587/transele.E94.C.1212},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays
T2 - IEICE TRANSACTIONS on Electronics
SP - 1212
EP - 1219
AU - Chul Bum KIM
AU - Doo Hyung WOO
AU - Byung Hyuk KIM
AU - Hee Chul LEE
PY - 2011
DO - 10.1587/transele.E94.C.1212
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2011
AB - This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 µm standard CMOS process for a 150
ER -
English
