IEICE TRANSACTIONS on Information
A Self-Timed SRAM Design for Average-Case Performance
Summary :
This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.
- Publication
- IEICE TRANSACTIONS on Information Vol.E94-D No.8 pp.1547-1556
- Publication Date
- 2011/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E94.D.1547
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Keyword
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Je-Hoon LEE, Young-Jun SONG, Sang-Choon KIM, "A Self-Timed SRAM Design for Average-Case Performance" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 8, pp. 1547-1556, August 2011, doi: 10.1587/transinf.E94.D.1547.
Abstract: This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1547/_p
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@ARTICLE{e94-d_8_1547,
author={Je-Hoon LEE, Young-Jun SONG, Sang-Choon KIM, },
journal={IEICE TRANSACTIONS on Information},
title={A Self-Timed SRAM Design for Average-Case Performance},
year={2011},
volume={E94-D},
number={8},
pages={1547-1556},
abstract={This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.},
keywords={},
doi={10.1587/transinf.E94.D.1547},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - A Self-Timed SRAM Design for Average-Case Performance
T2 - IEICE TRANSACTIONS on Information
SP - 1547
EP - 1556
AU - Je-Hoon LEE
AU - Young-Jun SONG
AU - Sang-Choon KIM
PY - 2011
DO - 10.1587/transinf.E94.D.1547
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2011
AB - This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.
ER -
English
