A 0.18 µm CMOS 12 Gb/s 10-PAM Serial Link Transmitter
Summary :
A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.11 pp.1787-1793
- Publication Date
- 2011/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1787
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Bongsub SONG, Kwangsoo KIM, Jinwook BURM, "A 0.18 µm CMOS 12 Gb/s 10-PAM Serial Link Transmitter" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 11, pp. 1787-1793, November 2011, doi: 10.1587/transele.E94.C.1787.
Abstract: A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1787/_p
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@ARTICLE{e94-c_11_1787,
author={Bongsub SONG, Kwangsoo KIM, Jinwook BURM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.18 µm CMOS 12 Gb/s 10-PAM Serial Link Transmitter},
year={2011},
volume={E94-C},
number={11},
pages={1787-1793},
abstract={A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.},
keywords={},
doi={10.1587/transele.E94.C.1787},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - A 0.18 µm CMOS 12 Gb/s 10-PAM Serial Link Transmitter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1787
EP - 1793
AU - Bongsub SONG
AU - Kwangsoo KIM
AU - Jinwook BURM
PY - 2011
DO - 10.1587/transele.E94.C.1787
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2011
AB - A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.
ER -
English
