Frequencies around 300GHz offer extremely broad atmospheric transmission window with relatively low losses of up to 10dB/km and can be regarded as the ultimate platform for ultrahigh-speed wireless communications with near-fiber-optic data rates. This paper reviews technical challenges and recent advances in integrated circuits targeted at communications using these and nearby “terahertz (THz)” frequencies. Possible new applications of THz wireless links that are hard to realize by other means are also discussed.

In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm2 core area with 82.6mW power consumption at 122.88MHz clock frequency.

Optical label processing is expected to reduce power consumption in label switching network nodes. Previously, we proposed passive waveguide circuits for the recognition of BPSK labels with a theoretically infinite contrast ratio. The recognizable label number was limited to four and eight for 4-bit and 8-bit BPSK labels, respectively. In this paper, we propose methods to increase the recognizable label number. The proposed circuits can recognize eight and sixteen labels of 4-bit BPSK codes with a contrast ratio of 4.00 and 2.78, respectively. As 8-bit BSPK codes, 64, 128, and 256 labels can be recognized with a contrast ratio of 4.00, 2.78, and 1.65, respectively. In recognition of all encoded labels, that is, 16 and 256 labels for 4-bit and 8-bit BPSK labels, a reference signal is employed to identify the sign of the optical output signals. The effect of phase deviation and loss along the optical waveguides of the devices is also discussed.

We have derived the physics-based equivalent circuit model of a semiconductor-integrated bow-tie antenna (BTA) for expressing its impedance and radiation characteristics as a terahertz transmitter. The equivalent circuit branches and components, consisting of 16 RLC parameters are determined based on electromagnetic simulations. All the values of the circuit elements are identified using the particle swarm optimization (PSO) that is one of the modern multi-purpose optimization methods. Moreover, each element value can also be explained by the structure of the semiconductor-integrated BTA, the device size, and the material parameters.

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.

This paper describes an equivalent circuit analysis of a meta-surface using a double-layered patch-type frequency-selective surface (FSS); the analysis considers the coupling between FSSs. Two types of double-layered structures are examined. One is a stacked structure and the other is an alternated structure. The results calculated using the equivalent circuit are in agreement with the results of the FDTD analysis. In addition, it is clarified that the stacked and alternated structures exhibit the common mode and the differential mode coupling, respectively. Moreover, experiments support analysis results for both stacked and alternated structures.

This paper presents a wideband differential amplifier operating at 141GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 20dB and a 3-dB bandwidth of 22GHz are achieved. It consumes 75mW from a 0.94-V voltage supply. The die area with balun and pads is 945×842µm2 and the size of the core not including input/output matching networks is 201×284µm2. The small core area is made possible by using a refined “fishbone” layout technique.

Circuit performance of SiC-MOSFET-based bidirectional isolated DC/DC converters is investigated based on circuit simulation with the physically accurate compact device model HiSIM_HV. It is demonstrated that the combined optimization of the MOSFETs Ron and of the inductances in the transformer can enable a conversion efficiency of more than 97%. The simulation study also verifies that the possible efficiency improvements are diminished due to the MOSFET-performance degradation, namely the carrier-mobility reduction, which results in a limitation of the possible Ron reduction. It is further demonstrated that an optimization of the MOSFET-operation conditions is important to utilize the resulting higher MOSFET performance for achieving additional converter efficiency improvements.

Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.

Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.

To provide basic considerations for the realization of method for suppressing the EMI from differential-paired lines on flexible printed circuits (FPC), the characteristics of the SI performance and shielding effectiveness (SE) of shielded-flexible printed circuits for differential-signaling are investigated in this paper experimentally and by a numerical modeling. Firstly, transmission characteristics of TDR measurement and frequency response of |Sdd21| are discussed, from view point of signal integrity. Secondly, as the characteristics of the SE performance for EMI, frequency responses of magnetic field are investigated. Although placement of conductive shield near the paired-lines decreases characteristics impedance, |Sdd21| for the “with Cu 5.5 µm-thickness copper shield” is not deteriorated compared with “without shield” and sufficient SE performance for magnetic field can be established. But, thin-shield deteriorates SI as well as SE performances. The frequency response of |Sdd21| at higher frequencies for the “Ag 0.1 µm” case has the steep loss roll off. A reflection loss resulted from impedance-mismatching is not dominant factor of the losses. The dominant factor may be magnetic field leakage due to very thin-conductive shield.

A frequency-reconfigurable dipole antenna, whose dual resonant frequencies are independently controlled, is introduced. The antenna's conductor consists of radiating conductors, lumped and distributed elements, and varactors. To design the antenna, current distribution, input impedance, and radiation power including higher-order modes, are analyzed for a narrow-angle sectorial antenna embedded with passive elements. To derive the formulae used, radiation power is analyzed in two ways: using Chu's equivalent circuit and the multipole expansion method. Numerical estimations of electrically small antennas show that dual-band antennas are feasible. The dual resonant frequencies are controlled with the embedded series and shunt inductors. A dual-band antenna is fabricated, and measured input impedances agree well with the calculated data. With the configuration, an electrically small 2.5-/5-GHz dual-band reconfig-urable antenna is designed and fabricated, where the reactance values for the series and shunt inductors are controlled with varactors, each connected in series to the inductors. Varying the voltages applied to the varactors varies the measured upper and lower resonant frequencies between 2.6 and 2.9GHz and between 5.1 and 5.3GHz, where the other resonant frequency is kept almost identical. Measured radiation patterns on the H-plane are almost omni-directional for both bands.

This paper presents a new approach for circuit matching using signatures. We have defined a signature based on topology of the fanin cones of the circuit elements. Given two circuits, first we find all the circuit elements with unique signature between the two input circuits. After that, we try to expand the matching area by our expansion rules as much as possible. We iteratively find the unique matches and expand the matching area until no further matching is possible. Our experiments on IWLS2005 benchmark suite show that our method is able to find the perfect matching between two 160,000-gate IP in 5 minutes. In addition, our method is more than one order of magnitude faster than our previous signature-based matching method, while the size of the matched area is comparable or larger.

In this study, a well-shaped microelectrode array (MEA) for fabricating a high-density complementary metal-oxide semiconductor amperometric electrochemical sensor array was designed and verified. By integrating an auxiliary electrode with the well-shaped structure of the MEA, the footprint was reduced and high density and high resolution were also achieved. The results of three-dimensional electrochemical simulations confirmed the effectiveness of the proposed MEA structure and possibility of increasing the density to four times than that achieved by the conventional two-dimensional structure.

It is known that, using just a deck of cards, an arbitrary number of parties with private inputs can securely compute the output of any function of their inputs. In 2009, Mizuki and Sone constructed a six-card COPY protocol, a four-card XOR protocol, and a six-card AND protocol, based on a commonly used encoding scheme in which each input bit is encoded using two cards. However, up until now, there are no known results to construct a set of COPY, XOR, and AND protocols based on a two-card-per-bit encoding scheme, which all can be implemented using only four cards. In this paper, we show that it is possible to construct four-card COPY, XOR, and AND protocols using polarizing plates as cards and a corresponding two-card-per-bit encoding scheme. Our protocols use a minimum number of cards in the setting of two-card-per-bit encoding schemes since four cards are always required to encode the inputs. Moreover, we show that it is possible to construct two-card COPY, two-card XOR, and three-card AND protocols based on a one-card-per-bit encoding scheme using a common reference polarizer which is a polarizing material accessible to all parties.

We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.

A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.

Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.

In this paper, we report the design of an organic thin-film transistor (OTFT) driver circuit for the actuator of an organic fluid pump, which can be integrated in a portable-size fully-organic artificial lung. Compared to traditional pump designs, lightness, compactness and scalability are achieved by adopting a creative pumping mechanism with a completely organic-material-based system concept. The transportable fluid volume is verified to be flexibly adjustable, enabling on-demand controllability and scalability of the pump's fluid-flow rate. The simulations, based on an accurate surface-potential OTFT compact model, demonstrate that the necessary driving waveforms can be efficiently generated and adjusted to the actuator requirements. At the actuator-driving-circuit frequency of 0.98Hz, an all-organic fluid pump with 40cm length and 0.2cm height is able to achieve a flow rate of 0.847L/min, which satisfies the requirements for artificial-lung assist systems to a weakened normal lung.