IEICE TRANSACTIONS on Electronics
RSFQ 4-bit Bit-Slice Integer Multiplier
Summary :
A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.6 pp.697-702
- Publication Date
- 2016/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.697
- Type of Manuscript
- Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
- Category
Authors
Guang-Ming TANG
Kyoto University
Kazuyoshi TAKAGI
Kyoto University
Naofumi TAKAGI
Kyoto University
Keyword
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Guang-Ming TANG, Kazuyoshi TAKAGI, Naofumi TAKAGI, "RSFQ 4-bit Bit-Slice Integer Multiplier" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 6, pp. 697-702, June 2016, doi: 10.1587/transele.E99.C.697.
Abstract: A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.697/_p
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@ARTICLE{e99-c_6_697,
author={Guang-Ming TANG, Kazuyoshi TAKAGI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={RSFQ 4-bit Bit-Slice Integer Multiplier},
year={2016},
volume={E99-C},
number={6},
pages={697-702},
abstract={A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.},
keywords={},
doi={10.1587/transele.E99.C.697},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - RSFQ 4-bit Bit-Slice Integer Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 697
EP - 702
AU - Guang-Ming TANG
AU - Kazuyoshi TAKAGI
AU - Naofumi TAKAGI
PY - 2016
DO - 10.1587/transele.E99.C.697
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2016
AB - A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.
ER -
English
