The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.

The recent rapid increase in the scale of superconducting quantum computing systems greatly increases the demand for qubit control by digital circuits operating at qubit temperatures. In this paper, superconducting digital circuits, such as single-flux quantum and adiabatic quantum flux parametron circuits are described, that are promising candidates for this purpose. After estimating their energy consumption and speed, a conceptual overview of the superconducting electronics for controlling a multiple-qubit system is provided, as well as some of its component circuits.

We have studied on thermally assisted nano-structured transistors made of superconductor ultra-thin films. These transistors potentially work as interface devices for Josephson-CMOS (complementary metal oxide semiconductor) hybrid memory systems, because they can generate a high output voltage of sub-V enough to drive a CMOS transistor. In addition, our superconductor transistors are formed with very fine lines down to several tens of nm in widths, leading to very small foot print enabling us to make large capacity hybrid memories. Our superconductor transistors are made with niobium titanium nitride (NbTiN) thin films deposited on thermally-oxidized silicon substrates, on which other superconductor circuits or semiconductor circuits can be formed. The NbTiN thickness dependence of the critical temperature and of resistivity suggest thermally activated vortex or anti-vortex behavior in pseudo-two-dimensional superconducting films plays an important role for the operating principle of the transistors. To show the potential that the transistors can drive MOS transistors, we analyzed the driving ability of the superconductor transistors with HSPICE simulation. We also showed the turn-on behavior of a MOS transistor used for readout of a CMOS memory cell experimentally. These results showed the high potential of superconductor transistors for Josephson-CMOS hybrid memories.

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.

We present our design and operation of a 6-bit quasi-triangle voltage waveform generator comprising three circuit blocks; an improved variable Pulse Number Multiplier (variable-PNM), a Code Generator (CG), and a Double-Flux-Quantum Amplifier (DFQA). They are integrated into a single chip using a niobium Josephson junction technology. While the multiplication factor of our previous m-bit variable-PNM was limited between 2m-1 and 2m, that of the improved one is extended between 1 and 2m. Correct operations of the 6-bit variable-PNM are confirmed in low-speed testing with respect to the codes from the CG, whereas generation of a 6-bit, 0.20mVpp quasi-triangle voltage waveform is demonstrated with the 10-fold DFQA in high-speed testing.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.