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Fabrication Process for Superconducting Digital Circuits
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Summary :
This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E104-C No.9 pp.405-410
- Publication Date
- 2021/09/01
- Publicized
- 2021/03/03
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2020SUI0002
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Fabrication of Superconductor Devices; Key Technology in Superconductor Electronics)
- Category
Authors
Mutsuo HIDAKA
AIST
Shuichi NAGASAWA
AIST
Keyword
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Mutsuo HIDAKA, Shuichi NAGASAWA, "Fabrication Process for Superconducting Digital Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 9, pp. 405-410, September 2021, doi: 10.1587/transele.2020SUI0002.
Abstract: This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020SUI0002/_p
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@ARTICLE{e104-c_9_405,
author={Mutsuo HIDAKA, Shuichi NAGASAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fabrication Process for Superconducting Digital Circuits},
year={2021},
volume={E104-C},
number={9},
pages={405-410},
abstract={This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.},
keywords={},
doi={10.1587/transele.2020SUI0002},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - Fabrication Process for Superconducting Digital Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 405
EP - 410
AU - Mutsuo HIDAKA
AU - Shuichi NAGASAWA
PY - 2021
DO - 10.1587/transele.2020SUI0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2021
AB - This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.
ER -
English
