IEICE TRANSACTIONS on Information
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Summary :
In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.
- Publication
- IEICE TRANSACTIONS on Information Vol.E99-D No.11 pp.2723-2733
- Publication Date
- 2016/11/01
- Publicized
- 2016/08/16
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2015EDP7273
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Widiant
Tokushima University
Masaki HASHIZUME
Tokushima University
Shohei SUENAGA
Tokushima University
Hiroyuki YOTSUYANAGI
Tokushima University
Akira ONO
Kagawa National College of Technology
Shyue-Kung LU
National Taiwan University of Science and Technology
Zvi ROTH
Florida Atlantic University
Keyword
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Widiant, Masaki HASHIZUME, Shohei SUENAGA, Hiroyuki YOTSUYANAGI, Akira ONO, Shyue-Kung LU, Zvi ROTH, "A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs" in IEICE TRANSACTIONS on Information,
vol. E99-D, no. 11, pp. 2723-2733, November 2016, doi: 10.1587/transinf.2015EDP7273.
Abstract: In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2015EDP7273/_p
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@ARTICLE{e99-d_11_2723,
author={ Widiant, Masaki HASHIZUME, Shohei SUENAGA, Hiroyuki YOTSUYANAGI, Akira ONO, Shyue-Kung LU, Zvi ROTH, },
journal={IEICE TRANSACTIONS on Information},
title={A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs},
year={2016},
volume={E99-D},
number={11},
pages={2723-2733},
abstract={In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.},
keywords={},
doi={10.1587/transinf.2015EDP7273},
ISSN={1745-1361},
month={November},}
Copy
TY - JOUR
TI - A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
T2 - IEICE TRANSACTIONS on Information
SP - 2723
EP - 2733
AU - Widiant
AU - Masaki HASHIZUME
AU - Shohei SUENAGA
AU - Hiroyuki YOTSUYANAGI
AU - Akira ONO
AU - Shyue-Kung LU
AU - Zvi ROTH
PY - 2016
DO - 10.1587/transinf.2015EDP7273
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E99-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2016
AB - In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.
ER -
English
