In this paper, dependency of transmission loss of shielded-flexible printed circuits (FPC) for differential-signaling on thickness of conductive shield is studied by numerical modeling based on an equivalent circuit model compared with the experimental results. Especially, the transmission loss due to the thin conductive shield is focused. The insufficient shielding performance for near magnetic field decreases the resistance due to the thin conductive shield. It is shown that the resistance due to the thin conductive shield at lower frequencies is smaller than that in the “thick conductive shield” case.

This paper introduces a formation method for 3-dimensional 6 ch.×6 ch. shuffling structures with graded-index (GI) circular core in a multimode polymer optical waveguide for optical printed circuit boards (OPCBs) using a unique photomask-free fabrication technique named the Mosquito method. The interchannel pitch of the fabricated waveguides is 250µm, where all the channels consist of both horizontal and vertical bending structures and the last 6 channels in parallel cross over the first 6 channels. We also report 3-dimensional S-shaped polymer waveguides. In the S-shaped waveguides, the first and last 6 channels with both horizontal and vertical core bending composing the above 3-dimensional shuffling waveguide are separated, in order to evaluate the effect of over-crossing on the loss. It is experimentally confirmed that there is no excess insertion loss due to the shuffling structure in the 3-D shuffling waveguide. The evaluated crosstalk of the 3-D shuffling waveguide is lower than -30dB. The 3-D shuffling waveguide proposed in this paper will be a promising component to achieve high bandwidth density wiring for on-board optical interconnects.

To meet the demand for continuous increase in data traffic, full usage of polarization freedom of light is becoming inevitable in the next-generation optical communication and datacenter networks. In particular, Stokes-vector modulation direct-detection (SVM-DD) formats are expected as potentially cost-effective method to transmit multi-level signals without using costly coherent transceivers in the short-reach links. For the SVM-DD formats to be practical, both the transmitter and receiver need to be substantially simpler, smaller, and lower-cost as compared to coherent counterparts. To this end, we have recently proposed and demonstrated novel SV modulator and receiver circuits realized on monolithic InP platforms. With compact non-interferometric configurations, relatively simple fabrication procedures, and compatibility with other active photonic components, the proposed devices should be attractive candidate in realizing low-cost monolithic transceivers for SVM formats. In this paper, we review our approaches as well as recent progresses and provide future prospects.

A penta-band antenna based on the mu-negative transmission line is presented for radio frequency (RF) energy harvesting application. The antenna utilizes five radiation modes; two quarter wavelength resonances, three quarter wavelength resonance, zeroth order resonance, and first order resonance. The parasitic radiating strip antenna generates quarter wavelength resonance radiation. The dual band antenna based on two unit cell mu-negative (MNG) transmission line gives birth to the zeroth order resonance (ZOR) mode and the first order resonance (FOR) mode. The parasitic radiating strip and dual band antenna based on two unit mu-negative (MNG) transmission line are magnetically coupled by a feed monopole with gap. This feed monopole, simultaneously, radiates at quarter and three quarter wavelength resonance frequency to cover the other bands. The multi-mode coupling mechanism of this penta-band antenna is well modeled by our derived equivalent circuit. The measured radiation efficiencies are more than 87% over the entire penta-band.

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

The microfabrication technique based on SR (Synchrotron Radiation) direct etching process has recently been applied to construct PTFE microstructures. This paper attempts to fabricate an integrated PTFE-filled waveguide Butler matrix for short millimeter-wave by SR direct etching. First, a cruciform 3-dB directional coupler and an intersection circuit (0-dB coupler) are designed at 180 GHz. Then, a 4×4 Butler matrix with horn antennas is designed and fabricated. Finally, the measured radiation patterns of the Butler matrix are shown.

We present a concept of an advanced rapid single-flux-quantum (RSFQ) logic circuit family using the combination of 0-shifted and π-shifted Josephson junctions. A π-shift in the current-phase relationship can be obtained in several types of Josephson junctions, such as Josephson junctions containing a ferromagnet barrier layer, depending on its thickness and temperature. We use a superconducting quantum interference devices composed of a pair of 0- and π-shifted Josephson junctions (0-π SQUIDs) as a basic circuit element. Unlike the conventional RSFQ logic, bistability is obtained by spontaneous circular currents without using a large superconductor loop, and the state can be flipped by smaller driving currents. These features lead to energy- and/or space-efficient logic gates. In this paper, we show several example circuits where we represent signals by flips of the states of a 0-π SQUID. We obtained successful operation of the circuits from numerical simulation.

We have studied on thermally assisted nano-structured transistors made of superconductor ultra-thin films. These transistors potentially work as interface devices for Josephson-CMOS (complementary metal oxide semiconductor) hybrid memory systems, because they can generate a high output voltage of sub-V enough to drive a CMOS transistor. In addition, our superconductor transistors are formed with very fine lines down to several tens of nm in widths, leading to very small foot print enabling us to make large capacity hybrid memories. Our superconductor transistors are made with niobium titanium nitride (NbTiN) thin films deposited on thermally-oxidized silicon substrates, on which other superconductor circuits or semiconductor circuits can be formed. The NbTiN thickness dependence of the critical temperature and of resistivity suggest thermally activated vortex or anti-vortex behavior in pseudo-two-dimensional superconducting films plays an important role for the operating principle of the transistors. To show the potential that the transistors can drive MOS transistors, we analyzed the driving ability of the superconductor transistors with HSPICE simulation. We also showed the turn-on behavior of a MOS transistor used for readout of a CMOS memory cell experimentally. These results showed the high potential of superconductor transistors for Josephson-CMOS hybrid memories.

The impedance expansion method (IEM), which was previously proposed by the authors, is a circuit-modeling technique for electrically-very-small devices. The equivalent circuits derived by the IEM include dependent voltage sources proportional to the powers of the frequency. However, the previous report did not describe how circuit simulators could realize such dependent voltage sources. This paper shows how this can be achieved by approximating the equivalent circuit using only passive elements.

A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 95.70dB is achieved while a sinusoid -1dBFS input is sampled at 60MS/s for the bandwidth is BW=470kHz. The power consumption of the analog part in the modulator is 1.67mW while the supply voltage is 1.2V.

This paper proposes a circuit modeling technique for electrically-very-small devices, e.g. electrodes for intrabody communications, coils for wireless power transfer systems, high-frequency transformers, etc. The proposed technique is based on the method of moments and can be regarded as an improved version of the partial element equivalent circuit method.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

Automatic design of analog circuits using a programmed algorithm is in great demand because optimal analog circuit design in a short time is required due to the limited development time. Although an automatic design using equation-based method can design simple circuits fast and accurately, it cannot solve complex circuits. On the other hand, an automatic design using optimization algorithm such as Ant Colony Optimization, Genetic Algorithm, and so on, can design complex circuits. However, because these algorithms are based on the stochastic optimization technique and determine the circuit parameters at random, a lot of circuits which do not operate in principle are generated and simulated to find the circuit which meets specifications. In this paper, to reduce the search space and the redundant simulations, automatic design using both equation-based method and a genetic algorithm is proposed. The proposed method optimizes the bias circuit blocks using the equation-based method and signal processing blocks using Genetic Algorithm. Simulation results indicate that the evaluation value which considers the trade-off of the circuit specification is larger than the conventional method and the proposed method can design 1.4 times more circuits which satisfy the minimum requirements than the conventional method.

As devices continue to shrink, the parameter shift due to process variation and aging effects has an increasing impact on the circuit yield and reliability. However, predicting how long a circuit can maintain its design yield above the design specification is difficult because the design yield changes during the aging process. Moreover, performing Monte Carlo (MC) simulation iteratively during aging analysis is infeasible. Therefore, most existing approaches ignore the continuity during simulations to obtain high speed, which may result in accumulation of extrapolation errors with time. In this paper, an incremental simulation technique is proposed for lifetime yield analysis to improve the simulation speed while maintaining the analysis accuracy. Because aging is often a gradual process, the proposed incremental technique is effective for reducing the simulation time. For yield analysis with degraded performance, this incremental technique also reduces the simulation time because each sample is the same circuit with small parameter changes in the MC analysis. When the proposed dynamic aging sampling technique is employed, 50× speedup can be obtained with almost no decline accuracy, which considerably improves the efficiency of lifetime yield analysis.

A 15GHz-band 4-channel transmit/receive RF core-chip is presented for high SHF wide-band massive MIMO in 5G. In order to realize small RF frontend for 5G base stations, both 6bit phase shifters (PS) and 0.25 dB resolution variable gain amplifiers (VGA) are integrated in TX and RX paths of 4-channels on the chip. A PS calibration technique is applied to compensate the error of 6bit PS caused by process variations. A common gate current steering topology with tail current control is used for VGA to enhance the gain control accuracy. The 15GHz-band RF core-chip fabricated in 65 nm CMOS process achieved phase control error of 1.9deg. rms., and amplitude control error of 0.23 dB. rms.

This paper presents a fast and large-scale optical circuit-switch architecture for intra-datacenter applications that uses a combination of space switches and wavelength-routing switches are utilized. A 1,440 × 1,440 optical switch is designed with a fast-tunable laser, 8×8 delivery-and-coupling switch, and a 180×180 wavelength-routing switch. We test the bit-error-ratio characteristics of all ports of the wavelength-routing switch using 180-wavelength 10-Gbps signals in the full C-band. The worst switching time, 498 microseconds, is confirmed and all bit-error ratios are acceptable.

In this paper, we propose a design method of compact multi-way Wilkinson power divider with a multiband operation for size reduction and band broadening. The proposed divider consists of multisection LC-ladder circuits in the division arms and isolation circuits between the output ports. To validate design procedures, we fabricated a trial divider at VHF band. The circuit layout of the trial divider was decided by using an electromagnetic simulator (Sonnet EM). Because the proposed divider consists of lumped element circuits, we can realize great miniaturization of a circuit area compared to that of the conventional Wilkinson power divider. The circuit size of the trial divider is 35 mm square. The measurement results for the trial divider by using a vector network analyzer indicates a relative bandwidth of about 60% under -17 dB reflection, flat power division within ±0.1 dB, and very low phase imbalances under 1.0 degree over the wide frequency range.

This paper proposes a read-only memory driving circuit for RFID tags based on a-IGZO thin-film transistors. The circuit consists of a Johnson counter and monotype complementary gates. By utilizing complementary signals to drive a decoder based on monotype complementary gates, the propagation delay can be decreased and the redundant current can be reduced. The Johnson counter reduces the number of registers. The new circuit can effectively avoid glitch generation, and reduce circuit power consumption and delay.

In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.

This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p≥3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(pm) multipliers for different p-values. In addition, we evaluate the performance of three types of GF(2m) multipliers and typical GF(pm) multipliers (p≥3) empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(pm) having extension degrees greater than 128.