IEICE TRANSACTIONS on Electronics
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring
Summary :
In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.9 pp.736-745
- Publication Date
- 2017/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.736
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Tomohiko YANO
The University of Tokyo
Toru NAKURA
The University of Tokyo
Tetsuya IIZUKA
The University of Tokyo
Kunihiro ASADA
The University of Tokyo
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Tomohiko YANO, Toru NAKURA, Tetsuya IIZUKA, Kunihiro ASADA, "A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 9, pp. 736-745, September 2017, doi: 10.1587/transele.E100.C.736.
Abstract: In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.736/_p
Copy
@ARTICLE{e100-c_9_736,
author={Tomohiko YANO, Toru NAKURA, Tetsuya IIZUKA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring},
year={2017},
volume={E100-C},
number={9},
pages={736-745},
abstract={In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.},
keywords={},
doi={10.1587/transele.E100.C.736},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring
T2 - IEICE TRANSACTIONS on Electronics
SP - 736
EP - 745
AU - Tomohiko YANO
AU - Toru NAKURA
AU - Tetsuya IIZUKA
AU - Kunihiro ASADA
PY - 2017
DO - 10.1587/transele.E100.C.736
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2017
AB - In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.
ER -
English
