We propose a pre-T event-triggered controller (ETC) for the stabilization of a chain of integrators. Our per-T event-triggered controller is a modified event-triggered controller by adding a pre-defined positive constant T to the event-triggering condition. With this pre-T, the immediate advantages are (i) the often complicated additional analysis regarding the Zeno behavior is no longer needed, (ii) the positive lower bound of interexecution times can be specified, (iii) the number of control input updates can be further reduced. We carry out the rigorous system analysis and simulations to illustrate the advantages of our proposed method over the traditional event-triggered control method.

We propose a zero-order-hold triggered control for a chain of integrators with an arbitrary sampling period. We analytically show that our control scheme globally asymptotically stabilizes the considered system. The key feature is that the pre-specified sampling period can be enlarged as desired by adjusting a gain-scaling factor. An example with various simulation results is given for clear illustration.

In this letter, we study the adaptive regulation problem for a chain of integrators in which there are different individual delays in measured feedback states for a controller. These delays are considered to be unknown and time-varying, and they can be arbitrarily fast-varying. We analytically show that a feedback controller with a dynamic gain can adaptively regulate a chain of integrators in the presence of unknown individual state delays. A simulation result is given for illustration.

We consider a regulation problem for an uncertain chain of integrators with an unknown time-varying delay in the input. To deal with uncertain parameters and unknown delay, we propose an adaptive event-triggered controller with a dynamic gain. We show that the system is globally regulated and interexecution times are lower bounded. Moreover, we show that these lower bounds can be enlarged by adjusting a control parameter. An example is given for clear illustration.

We consider an asymptotic stabilization problem for a chain of integrators by using an event-triggered controller. The times required between event-triggered executions and controller updates are uncertain, time-varying, and not necessarily small. We show that the considered system can be asymptotically stabilized by an event-triggered gain-scaling controller. Also, we show that the interexecution times are lower bounded and their lower bounds can be manipulated by a gain-scaling factor. Some future extensions are also discussed. An example is given for illustration.

This paper presents a 6th-order quadrature bandpass delta sigma AD modulator (QBPDSM) with 2nd-order image rejection using dynamic amplifier and noise coupling (NC) SAR quantizer embedded by passive adder for the application of wireless communication system. A novel complex integrator using dynamic amplifier is proposed to improve the energy efficiency of the QBPDSM. The NC SAR quantizer can realize an additional 2nd-order noise shaping and 2nd-order image rejection by the digital domain noise coupling technique. As a result, the 6th-order QBPDSM with 2nd-order image rejection is realized by two complex integrators using dynamic amplifier and the NC SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed QBPDSM in 90nm CMOS technology. Simulated SNDR of 76.30dB is realized while a sinusoid -3.25dBFS input is sampled at 33.3MS/s and the bandwidth of 2.083MHz (OSR=8) is achieved. The total power consumption in the modulator is 6.74mW while the supply voltage is 1.2V.

This paper presents a novel delta-sigma modulator that uses a switched-capacitor (SC) integrator with the structure of a finite impulse response (FIR) filter in a loop filter configuration. The delta-sigma analog-to-digital converter (ΔΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. Increasing the gain coefficient of the integrator in the loop filter configuration of the ΔΣADC suppresses the quantization noise that occurs in the signal band. However, there is a trade-off relationship between the integrator gain coefficient and system stability. The SC integrator, which contains an FIR filter, can suppress quantization noise in the signal band without requiring an additional operational amplifier. Additionally, it can realize a higher signal-to-quantization noise ratio. In addition, the poles that are added by the FIR filter structure can improve the system's stability. It is also possible to improve the flexibility of the pole placement in the system. Therefore, a noise transfer function that does not contain a large gain peak is realized. This results in a stable system operation. This paper presents the essential design aspects of a ΔΣADC with an FIR filter. Two types of simulation results are examined for the proposed first- and second-order, and these results confirm the effectiveness of the proposed architecture.

In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.

This paper is a sequel to [4] in which the system is generalized by including unknown time-varying delays in both states and input. Regarding the controller, the design of adaptive gain is simplified by including only x1 and u whereas full states are used in [4]. Moreover, it is shown that the proposed controller is also applicable to a class of upper triangular nonlinear systems. An example is given for illustration.

Mixed-signal integrated circuit design and simulation highly rely on behavioral models of circuit blocks. Such models are used for the validation of design specification, optimization of system topology, and behavioral synthesis using a description language, etc. However, automatic behavioral model generation is still in its early stages; in most scenarios designers are responsible for creating behavioral models manually, which is time-consuming and error prone. In this paper an automatic behavioral model generation method for switched-capacitor (SC) integrator is proposed. This technique is based on symbolic circuit modeling with approximation, by which parametric behavioral integrator model can be generated. Such parametric models can be used in circuit design subject to severe process variational. It is demonstrated that the automatically generated integrator models can accurately capture process variation effects on arbitrarily selected circuit elements; furthermore, they can be applied to behavioral simulation of SC Sigma-Delta modulators (SDMs) with acceptable accuracy and speedup. The generated models are compared to a recently proposed manually generated behavioral integrator model in several simulation settings.

We consider a chain of integrators system that has an uncertain delay in the input. Also, there is a measurement noise in the feedback channel that only noisy output is available. We develop a new output feedback control scheme along with amplification such that the ultimate bounds of all states and output of the controlled system can be made arbitrarily small. We note that the condition imposed on the sensor noise is quite general over the existing results such that the sensor noise is uncertain and is only required to be bounded by a known bound. The benefit of our control method is shown via an example.

For systems with a delay in the input, the predictor method has been often used in state feedback controllers for system stabilization or regulation. In this letter, we show that for a chain of integrators with even an unknown input delay, a much simpler and memoryless controller is a good candidate for system regulation. With an adaptive gain-scaling factor, the proposed state feedback controller can deal with an unknown time-varying delay in the input. An example is given for illustration.

This letter investigates the consensus problem for an undirected network of high-order integrators with an arbitrarily large communication delay. A consensus protocol with the low gain parameter that can eliminate an effect of time delay on the consensus problem is proposed newly. Moreover, it is proved that under some sufficient conditions, it can solve the consensus problem in the presence of an arbitrarily large communication delay. A simulation example is presented to verify the validness of the proposed design.

Sensor noise prevents the exact measurement of output, which makes it difficult to guarantee the ultimate bound of the actual output and states, which is smaller than the sensor noise amplitude. Even worse, the time-varying delay in the input does not guarantee the boundedness of the actual output and states under sensor noise. In this letter, our considered system is a chain of integrators in which time-varying delay exists in the input and there is an additive form of sensor noise in the output measurement. To guarantee the arbitrarily small ultimate bound of the actual output and states, we newly propose an adaptive output feedback controller whose gain is tuned on-line. The merits of our control method over the existing results are clearly shown in the example.

We consider an output feedback control problem of a chain of integrators under sensor noise. The sensor noise enters the output feedback channel in an additive form. A similar problem has been addressed most recently in [9], but their result has been developed only under AC sensor noise. We generalize the result of [9] by allowing the sensor noise to include both AC and DC components. With our new output feedback controller, we show that the ultimate bounds of all states can be made arbitrarily small. We show the generality of our result over [9] via an example.

A design methodology for implementation of low-noise switched-capacitor low-pass filter (SC LPF) with small capacitance spread is proposed. The proposed method is focused on the reduction of operational amplifier noise transfer gain at low frequencies and the reduction of total capacitance. A new SC LPF topology is proposed in order to adapt the correlated double sampling and charge scaling technique at the same time. Design examples show that proposed filter reduces the total capacitance by 65% or more compared to the conventional one without having significant increase in noise transfer gain.

In this letter, we consider a control problem of a chain of integrators where there is an uncertain delay in the input and sensor noise. This is an output feedback control result over [10] in which a state feedback control is suggested. The several generalized features are: i) output feedback control is developed instead of full state feedback control, ii) uncertain delay in the input is allowed, iii) all states are derived to be arbitrarily small under uncertain sensor noise.

In this letter, we consider a control problem of a chain of integrators by output feedback under sensor noise. First, we introduce a measurement output feedback controller which drives all states and output of the considered system to arbitrarily small bounds. Then, we suggest a measurement output feedback controller coupled with a switching gain-scaling factor in order to improve the transient response and retain the same arbitrarily small ultimate bounds as well. An example is given to show the advantage of the proposed control method.

A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.