A technique to reduce noise transfer functions (NTF) of switched-capacitor (SC) integrators without changing their signal transfer functions (STF) is proposed. The proposed technique based on a simple reconnection scheme of multiple sampling capacitors. It can be implemented into any SC integrators as long as they have a transfer delay. A design strategy is also given to reduce the effect of parasitic capacitors. An SC integrator with a small total capacitance and a low noise transfer gain based on the proposed technique is also proposed. For a given design example, the total capacitance and the simulated noise transfer gain of the proposed SC integrator are 37% and 90% less than the conventional one.

In this letter, we consider a control problem of a chain of integrators with a delay in the input under measurement feedback. While there are several control results for our considered system, they have not dealt with any of measurement feedback problems. Our proposed controller is coupled with a low-pass filter such that it can attenuate the sensor noise effect and reduce the ultimate bounds of the controlled systems states. Our result shows that the proposed method has clear benefit over the existing results.

A switched-capacitor integrator based on dynamic source follower amplifiers has been proposed. Integrator operation has been confirmed and analyzed by assuming 0.18-µm CMOS technology. The integrator can reduce the number of elements considerably compared with conventional ones using operational amplifiers. As a result, the power dissipation of proposed integrator can be reduced to approximately one-eighth that of conventional integrators. The integrator is applied to a second-order ΔΣ modulator, and its successful operation has been confirmed by transistor-level circuit simulation.

This paper proposes a robust state observer for multi-input multi-output LTI systems. Unknown inputs of polynomial form and high-frequency measurement noises are considered in the system model. The unknown inputs and the noises are not in the same form. Multiple integrations of both the observer error signal and the measurement output are used for the observer design. The existence condition of the proposed observer is shown to be the same as that of the proportional-integral (PI) observer. Computer simulations show the effectiveness of the proposed observer.

A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35 µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500 kHz to 280 MHz, with a correction error within 50%1% under 200 MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.

In this paper, an energy-collection-based non-coherent IR-UWB receiver allowing low complexity and low power consumption is proposed for short range data communication. The proposed receiver consists of an on-the-fly integrator, a 1-bit digital sampler, a pre-processor and a digital symbol synchronizer. The on-the-fly integrator for energy collection and the 1-bit digital sampler reduce complexity of IR-UWB system. Furthermore, with a simple digital filter in the pre-processing unit, SNR and robustness of the receiver against time-varying channel are enhanced. Also the receiver complexity is diminished by a simple scheme of symbol synchronization based on rough time information about incoming pulses, not requiring exact timing information. The performance of the proposed receiver is simulated based on IEEE 802.15.4a channel model and the algorithms are implemented and verified on a FPGA.

This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.

In this paper, we propose a voltage controlled oscillator (VCO) with up mode type Miller-integrator. The controlled voltage of this VCO can continuously change 0 V center in the positive and negative bidirection. Also, the relationship between control voltage and oscillating frequency shows the good linearity, and the calculated and the measured values agree well.

We consider the chains of integrators with nonlinear terms which allow state and input delays. We provide an output feedback controller which globally asymptotically stabilizes the given system under certain sufficient conditions. It turns out that the obtained result includes several existing results as particular cases. This point is shown through two applications of the main result. Also, industrial processes are presented to illustrate the practicability of our result.

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 µm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 µW with a 900 mV voltage supply.

A high-speed transconductance-C-opamp integrator using a current-feedback amplifier is proposed. The integrator has good frequency response compared with a conventional transconductance-C-opamp integrator using a voltage-feedback amplifier. The current-feedback amplifier shifts the second pole of the proposed integrator to the upper frequency. The frequency is proportional to the current gain of the current-feedback amplifier. The proposed integrator can eliminate effects of the parasitics at the output node of the transconductance since the voltage at the node is fixed. One of the circuit examples of the proposed integrator is shown. Its validity is confirmed through HSPICE simulations. The proposed integrator works as predicted up to 260 MHz.

Some new differential input ideal differentiator and integrator function circuits using the current feedback amplifier (CFA) device are presented. The time constant (τo) is tunable by the control voltage (Vc) of a multiplier element connected appropriately around the feedback loop. The CFA device port errors () have insignificant effects on (τo). Test results based on hardware implementation and macromodel simulation are included; the proposed circuits exhibited good high frequency response with low phase errors (θe 2) upto about 450 kHz.

The transfer characteristic of an integrator is affected by excess-phase shift caused by the parasitic capacitance. The phase compensation is obtained by introducing zeros to generate phase lead. This paper proposes a phase compensation technique for the differential signal input integrator. The proposed technique is employing feedforward signal current source. The fifth-order leapfrog Chebyshev low-pass filter with 0.5 dB passband ripple is designed using the integrator with the proposed phase compensation. Further, an autotuning phase compensation system using the proposed technique is realized by applying a PLL system. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator with the proposed phase compensation shows that excess-phase cancellation is obtained at various unity gain frequencies. The accurate filter characteristic of the fifth-order leapfrog filter is obtained by using the autotuning phase compensation system. The passband of the filter is improved over wide range of frequencies. The proposed technique is suitable for low voltage application.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

In current-mode signal processing, a companding integrator is attractive from the viewpoint of linearity under a low power supply voltage. In this paper, new instantaneous companding integrators using MOSFET's are proposed. The companding integrator utilizes a nature of MOSFET square law. HSPICE simulation results demonstrate several advantages of the proposed circuits.

This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

A novel phase compensation technique for feedback integrators is proposed. By the technique, a zero is obtained without employing extra capacitors. A design of an integrator for IC using the proposed technique is presented. The frequency of the parasitic pole is proportional to the unity gain frequency. It is shown that excess-phase cancellation is obtained at any unity gain frequency.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

In this paper, a new nonlinear integrator with positive phase shifts is proposed. Results of the digital simulation show that the nonlinear integrator has a better performance than the conventional one in a control system.