Recently, the low earth orbit satellite communications has been attracting much attention. These communications have many strong features, however, the communication performances are influenced by carrier frequency offset (CFO) and, particularly, it is hard to acquire the synchronization. A large number of publications have so far been made on the synchronization acquisition of DS/SS systems under CFO and most of them make use of the maximum likelihood decision in finding the maximum values of Fourier transform outputs. However, the implementations of Fourier transforms usually require high cost and large space. In this paper, we propose a new simple acquisition scheme using half-symbol differential decoding technique for DS/SS systems under CFO. This scheme makes use of the addition and subtraction of baseband signals and their delayed versions, (omitting Fourier transforms), together with integrations by recursive integrators, and thus resulting in much simpler implementation. In general, it is shown that the proposed scheme can acquire the code synchronization under carrier frequency offset with much smaller computational complexities and the sacrifice of longer acquisition time.

A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.

In this paper,novel techniques for designing Finite Impulse Response (FIR) digital integrators have been given. The design is based on analytical approach for computing the weights required in the structures. Exact mathematical formulas for computing these weights have been derived.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

This paper proposes a topology-independent predistortion for filters using integrators. This employs integrators having the same structure, the same-value elements and an electrically controllable unity-gain frequency and compensates for the deviation of frequency characteristics due to excess phase shifts of integrators without knowledge of a filter topology. The effectiveness of the proposed method is demonstrated through SPICE simulations.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

In this letter, we propose a simple voltage controlled oscillator (VCO) with circuitry combining a Miller integrator and an RS flip-flop circuit. With the VCO, the control voltage can be varied over a broad range, and the oscillation frequency varies in proportion to the control voltage. The maximum voltage is up to 1000 times the minimum, and the calculated design values and measured values agree well. This VCO can be applied to FM modulators, FSK modulators, and other systems.

A multi-stage noise-shaping (MASH) A/D converter combining an RC-integrator and a digital correction technique for high accuracy is described. Using 1.2-µm BiCMOS technology, we developed an A/D converter for digital audio with an S/N ratio of over 100 dB. This paper discusses the principles of MASH technology with an RC-integrator, the technique for correcting RC variation, and the experimental results obtained with a fabricated chip.

An integrator is quite a suitable active element for high-speed filters. The effect of its excess phase shifts, however, is severe in the case of high-Q filter realization. The deterioration due to the excess phase shifts cannot be avoided when only integrators are used as frequency-dependent elements like in leapfrog realization. This paper describes a design of second-order high-speed and high-Q filters with low sensitivity to excess phase shifts of integrators by adding a passive RC circuit. The proposed method can drastically reduce the effect due to the undesirable pole of an integrator, which is the cause of the excess phase shifts, compared to conventional filters using only integrators. As an example, a fourth-order bandpass filter with 5-MHz center frequency and Q=25 is implemented by the proposed method on a monolithic chip. The results obtained here show quite good agreement with the theoretical values. This demonstrates effectiveness of the proposed method and feasibility of high-speed and high-Q filters on a monolithic chip.

Up to present, some automatically tunable active RC filters have been proposed for the monolithic integrated continuous-time filters. In this paper a synthesis method of monolithic active RC filters is presented, whose characteristic is hardly dependent on temperature, supply voltage and so on, theoretically. First, this paper describes a variable integrator controlled by bias current. Second, a resistor controlled current source circuit (RCCS) is also proposed, which contains the voltage controlled current source (VCCS) being identical with that used in the realization of the integrator and whose current is controlled by an external resistor. The use of this VCCS in the RCCS can completely compensate the variation of the integrator characteristics. Finally, these circuits are applied to realize a third-order elliptic low-pass filter, which is simulated on PSPICE. From the simulations, we obtain excellent results as follows: The deviation of gains in the passband due to the variation of temperature with a range of -10 to 60 is within 0.02 dB; A total harmonic distortion with a 1 Vp-p input voltage at 100 kHz is less than 0.4% when the cut-off frequency is 1 MHz and the supply voltage is 5 V.