A 3V-30MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator
Summary :
A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1994-1999
- Publication Date
- 1997/10/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Kwang Sub YOON, Jai-Sop HYUN, "A 3V-30MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1994-1999, October 1997, doi: .
Abstract: A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1994/_p
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@ARTICLE{e80-a_10_1994,
author={Kwang Sub YOON, Jai-Sop HYUN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3V-30MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator},
year={1997},
volume={E80-A},
number={10},
pages={1994-1999},
abstract={A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A 3V-30MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1994
EP - 1999
AU - Kwang Sub YOON
AU - Jai-Sop HYUN
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.
ER -
English
