A low-voltage class-AB CMOS output stage with a tunable quiescent current control circuit is presented. It is based on a complementary common source. The quiescent current is detected by a compact circuit and can be adjusted by means of a control current without need to modify the transistor dimensions. The minimum supply voltage can be down to one threshold voltage plus two saturation voltages. It is suitable to drive low resistive loads. Simulation results are provided that are in agreement with expected characteristics.

An on-chip soft-start circuit based on a switched-capacitor for DC-DC switching regulator is presented. A ramp-voltage, which is generated by a switched-capacitor, is used to make pulse width slowly increase from zero, in order to eliminate the inrush current and the overshoot voltage during start-up. The post simulation results show that the regulator soft starts well with the proposed soft-start circuit.

Virtual Machine Placement (VMP) plays an important role in ensuring efficient resource provisioning of physical machines (PMs) and energy efficiency in Infrastructure as a Service (IaaS) data centers. Efficient server consolidation assisted by virtual machine (VM) migration can promote the utilization level of the servers and switch the idle PMs to sleep mode to save energy. The trade-off between energy and performance is difficult, because consolidation may cause performance degradation, even service level agreement (SLA) violations. A novel residual available capacity (RAC) resource model is proposed to resolve the VM selection and allocation problem from the cloud service provider (CSP) perspective. Furthermore, a novel heuristic VM selection policy for server consolidation, named Minimized Square Root available Resource (MISR) is proposed. Meanwhile, an efficient VM allocation policy, named Balanced Selection (BS) based on RAC is proposed. The effectiveness validation of the BS-MISR combination is conducted on CloudSim with real workloads from the CoMon project. Evaluation results of experiments show that the proposed combinationBS-MISR can significantly reduce the energy consumption, with an average of 36.35% compared to the Local Regression and Minimum Migration Time (LR-MMT) combination policy. Moreover, the BS-MISR ensures a reasonable level of SLAs compared to the benchmarks.

In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.

A new trigger circuit based on up/down counter is proposed. This trigger circuit consists of a up/down counter and a pulse conversion circuit. Compared with a trigger circuit based on 32-bit counter, the proposed trigger circuit occupies less circuit area and consumes less power consumption, while the trigger process can be inversed, increasing the controllability of the Trojan.

This paper proposes a read-only memory driving circuit for RFID tags based on a-IGZO thin-film transistors. The circuit consists of a Johnson counter and monotype complementary gates. By utilizing complementary signals to drive a decoder based on monotype complementary gates, the propagation delay can be decreased and the redundant current can be reduced. The Johnson counter reduces the number of registers. The new circuit can effectively avoid glitch generation, and reduce circuit power consumption and delay.

Let Fpm be the field of pm elements where p is an odd prime. In this letter, binary sequence pairs of period N=pm-1 are presented, where sequences are generated from the polynomial x2-c for any c Fpm{0}. The cross-correlation values of sequence pairs are completely determined, our results show that those binary sequence pairs have optimal three-level correlation.

A novel optical technique for the measurement of temperature is proposed. This is accomplished by depositing alternating 1/4 wave layers of silicon nitride and silicon-rich silicon nitride at the end of an optical fiber. These layers of alternating refractive index form the equivalent of a Bragg grating of a high temperature material. When the fiber and the Bragg grating are heated, the Bragg stack expands, and there is a change in the reflective peak wavelength of this wave stack. Thus, the wavelength of peak reflectivity is a function of temperature. Currently, the 15 nm spectral width of the Bragg stacks is achieved in our laboratory, which is conveniently monitored with a CCD solid state spectrometer and the temperature sensor probes can be also multiplexed at separated specific reflection wavelength. In the experiment, the temperatures in excess of 1,100 centigrade have been measured with a resolution of less than 3 centigrade degree.

Based on a reverse converter algorithm derived from the New Chinese Remainder Theorem I, an algorithm for sign detection of RNS {2n-1, 2n, 2n+1} is presented in this paper. The hardware of proposed algorithm can be implemented using two n-bit additions and one (n+1)-bit comparator. Comparing with the previous paper, the proposed algorithm has reduced the number of additions used in the circuit. The experimental results show that the proposed circuit achieves 17.3% savings in area for small moduli and 10.5% savings in area for large moduli on an average, with almost the same speed. The power dissipations obtain 12.6% savings in average.