IEICE TRANSACTIONS on Electronics
Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors
Summary :
In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.6 pp.727-729
- Publication Date
- 2016/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.727
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Lihao ZHONG
South China University of Technology
Ruohe YAO
South China University of Technology
Fei LUO
South China University of Technology
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Lihao ZHONG, Ruohe YAO, Fei LUO, "Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 6, pp. 727-729, June 2016, doi: 10.1587/transele.E99.C.727.
Abstract: In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.727/_p
Copy
@ARTICLE{e99-c_6_727,
author={Lihao ZHONG, Ruohe YAO, Fei LUO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors},
year={2016},
volume={E99-C},
number={6},
pages={727-729},
abstract={In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.},
keywords={},
doi={10.1587/transele.E99.C.727},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 727
EP - 729
AU - Lihao ZHONG
AU - Ruohe YAO
AU - Fei LUO
PY - 2016
DO - 10.1587/transele.E99.C.727
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2016
AB - In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.
ER -
English
