To improve immunity against process gradients, a common centroid constraint, in which every pair of capacitors should be placed symmetrically with respect to a common center point, is widely used. The pair of capacitors are derived by dividing some original capacitors into two halves. Xiao et al. proposed a method to obtain a placement which satisfies the common centroid constraints, but this method has a defect. In this paper, we propose a decoding algorithm to obtain a placement which satisfies common centroid constraints.

A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.

The equivalent circuit of aperture-coupled cavities filled with a lossy dielectric is considered by means of an eigenmode expansion technique founded on the segmentation concept. It is different from a series LCR resonant circuit, and the resistor which symbolizes the dielectric loss is connected to the capacitor in parallel. If the cavities are formed by a short-circuited oversize waveguide, then the input admittance can be represented by the product of a coupling factor to the connected waveguide port and the equivalent admittance of the short-circuited waveguide. The transmission line model is effective even if lossy wall effect and dielectric partially-loading effect are considered. As a result, three-dimensional eigenmode parameters, such as the resonant frequency and the Q-factor, become dispensable and the computational complexity for the cavity simulation in the field of microwave heating is dramatically reduced.

In this paper, we present a pure hardware implementation of the advanced encryption standard (AES) with 8-bit data path with both encryption/decryption abilities for applications of wireless network. To achieve the requirements of low area resource and high throughput performance, the 8-bit AES design overlaps the MixColumns (MC) and ShiftRows (SR), Inverse MixColumns (IMC) and Inverse ShiftRows (ISR) operations in order to reduce the required clock cycles and critical path delay of transformations involved. The combinations of SB with ISB, MC with IMC, and SR with ISR can effectively reduce the area cost of the AES realization. We implement the AES processor in an ASIC chip. The design has the area cost of 4.3 k-gates with throughput of 72Mbps which can meet the throughput requirement of IEEE 802.11g wireless network standard. From the experimental results, we observe that our AES design has better performance compared with other previous designs.

As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.

Pseudo Power Gating (Pseudo PG) is one of gate level power reduction methods for combinational circuits by stopping unnecessary input changes of gates. In Pseudo PG, an extra control signal might be added to a gate and other input changes of the gate are deactivated when the control signal takes the controlling value. To improve the power reduction capability, the paper newly introduces dual-stage Pseudo PG with advanced clustering algorithm where up to two extra control signals are added to a gate if effective. The advanced clustering algorithm selects the first control signal to be compatible with the second control signal based on the propagation of controlling condition via a path, with which candidates of controllable gates excluded by the maximum depth constraint can be controlled. Experimental results show that the proposed dual-stage Pseudo PG method has obtained 23.23% average power reduction with 5.28% delay penalty with respect to the original circuits, and has obtained 10.46% more power reduction with 2.75% delay penalty compared with respect to circuits applying the original single-stage Pseudo PG.

Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.

This paper propose a structure of standard cells where the P/N boundary ratio of each cell can be independently customized for near-threshold operation. Lowering the supply voltage is one of the most promising approaches for reducing the power consumption of VLSI circuit, however, this causes an increase of imbalance between rise and fall delays for cells having transistor stacks. Conventional cell library with fixed P/N boundary is not efficient to compensate this delay imbalance. Proposed structure achieves individual P/N boundary ratio optimization for each standard cell, therefore it cancels the imbalance between rise and fall delays at the expense of cell area. Proposed structure is verified using measured result of Ring Oscillator circuits and simulation result of benchmark circuits in 65nm CMOS. The experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.

A new theoretical formulation based on BIBO (Bounded Input Bounded Output) operators is proposed for a general feedback amplifier circuit. Several fundamental theorems are derived in this letter. The main theorem provides a basis for a realization of an inverse of a feedback-branch linear or nonlinear BIBO operator satisfying the associative law.

This paper describes how to design matching structures to improve the frequency characteristics of one-dimensional finite periodic structures. In particular, it deals with one-dimensional finite superlattices. A downhill simplex method is used to determine some of the structural parameters of the matching structure. Numerical examples show that this method is effective in improving the frequency characteristics of finite superlattices.

The linearity analysis of a passive mixer is presented. The distortion mechanism caused by switching operation of a MOS transistor is elucidated from the static and dynamic analysis of passive mixers. Furthermore, the maximum input and output level to keep linear operation and its required bias conditions are expressed by simple equations. The maximum linear output amplitude of the passive mixer is determined only by the local signal amplitude and it does not depend on input and output impedance. The calculated linearity performances agree well with simulated and measured results.

A two-dimensional negative refractive index material is proposed. The material has a bulky structure composed of dielectric prism cells with metal patterns. The material is expressed by an equivalent circuit. The propagation regions of two left-handed modes calculated from the equivalent circuit exist near the propagation regions obtained by electromagnetic simulation. It is confirmed by simulation that the incident plane wave goes into the material with low reflection by using the second left-handed mode and attaching metal conversion strips around the material. A negative refractive index slab lens with 15×9 cells is made to measure the field distribution of wave out of the lens. It is shown that the resolution of the slab lens exceeds the diffraction-limit.

In terms of the transmission-line theory, a general synthesis of a new class of optimum Chebyshev-type ultra-wideband bandpass (UWB) filter prototype composed of multistage stepped-impedance resonators (SIRs) and two short-circuited shunt stubs positioned at input- and output- ports is presented. By the comparison of the real and theoretical transfer functions, the design/characteristic equations are obtained for the design of the proposed filter prototype rather than the traditional design tables. The explicit expressions of one-stage and two-stage filters are then derived and reported. Accordingly, bandpass filters with an arbitrary FBW (Fractional Bandwidth) and passband ripple can be easily designed by solving the design equations. As an example, a 10-degree Chebyshev distributed filter (two-stage filter) with an FBW of 110% is synthesized to meet FCC's outdoor mask. The synthesized circuit model are confirmed by a commercial circuit simulator and then optimized by an EM simulator, fabricated in microstrip line and characterized by the network analyzer. The good agreements between the measured and predicted frequency responses validate the effectiveness of newly proposed filter prototype and the corresponding synthesis technique. In addition, the designed filter exhibits good characteristics of comparatively low insertion loss, quite sharp skirt, very flat group delay and good stopband (especially in lower one) as well. It should be also highlighted that, compared with the conventional filters composed merely of parallel-coupled SIRs or shunt short-circuit-stubs, the new prototype can reduce the overall length of the filter by more than 3/4λg. Moreover, in terms of the presented design technique, the proposed filter prototype can be also used to easily realize the UWB filters with an FBW even greater than 110%.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.

With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.

There is a relentless push for cost and size reduction in optical transmitters and receivers for fiber-optic links. Monolithically integrated optical chips in InP and Si may be a way to leap ahead of this trend. We discuss uses of integration technology to accomplish various telecommunications functions.

20-Gbps non return-to-zero (NRZ) – binary phase shift keying (BPSK) using the silicon Mach-Zehnder modulator is demonstrated and characterized. Measurement of a constellation diagram confirms successful modulation of 20-Gbps BPSK with the silicon modulator. Transmission performance is characterized in the measurement of bit-error-rate in accumulated dispersion range from -347 ps/nm to +334 ps/nm using SMF and a dispersion compensating fiber module. Optical signal-to-noise ratio required for bit-error-rate of 10-3 is 10.1 dB at back-to-back condition. It is 1.2-dB difference from simulated value. Obtained dispersion tolerance less than 2-dB power penalty for bit-error-rate of 10-3 is -220 ps/nm to +230 ps/nm. The symmetric dispersion tolerance indicates chirp-free modulation. Frequency chirp inherent in the modulation mechanism of the silicon MZM is also discussed with the simulation. The effect caused by the frequency chirp is limited to 3% shift in the chromatic dispersion range of 2 dB power penalty for BER 10-3. The effect inherent in the silicon modulation mechanism is confirmed to be very limited and not to cause any significant degradation in the transmission performance.