In recent years, the demand for low-power design has remained undiminished. In this paper, a pseudo power gating (SPG) structure using a normal logic cell is proposed to extend the power gating to an ultrafine grained region at the gate level. In the proposed method, the controlling value of a logic element is used to control the switching activity of modules computing other inputs of the element. For each element, there exists a submodule controlled by an input to the element. Power reduction is maximized by controlling the order of the submodule selection. A basic algorithm and a switching activity first algorithm have been developed to optimize the power. In this application, a steady maximum depth constraint is added to prevent the depth increase caused by the insertion of the control signal. In this work, various factors affecting the power consumption of library level circuits with the SPG are determined. In such factors, the occurrence of glitches increases the power consumption and a method to reduce the occurrence of glitches is proposed by considering the parity of inverters. The proposed SPG method was evaluated through the simulation of the netlist extracted from the layout using the VDEC Rohm 0.18 µm process. Experiments on ISCAS'85 benchmarks show that the reduction in total power consumption achieved is 13% on average with a 2.5% circuit delay degradation. Finally, the effectiveness of the proposed method under different primary input statistics is considered.

Gains of a roll force AGC (Automatic Gain Controller) have been calculated at the first locked-on-time by FSU (Finishing-mill Set-Up model) in hot strip mills and usually these values are not adjusted during the operating time. Consequently, this conventional scheme cannot cope with the continuous variation of system parameters and circumstance, though the gains can be changed manually with the aid of experts to prevent a serious situation such as inferior mass production. Hence, partially uncontrolled variation still remains on delivery thickness. This paper discusses an effective online algorithm which can adjust the gains of the existing control system by considering the effect of time varying variables. This algorithm improves the performance of the system without additional cost and guarantees the stability of the conventional system. Specifically, this paper reveals the major factors that cause the variation of strip and explores the relationship between AGC gains and the effects of those factors through the analysis of thickness signal which occupy different frequency bands. The proposed tuning algorithm is based on the above relationship and realized through ANFIS (Adaptive-Neuro-based Fuzzy Interface System) which is a very useful method because its fuzzy logics reflect the experiences of professionals about the uncertainty and the nonlinearity of the system. The effectiveness of the algorithm is shown by several simulations which are carried out by using the field data of POSCO corporation (South Korea).

Pseudo Power Gating (Pseudo PG) is one of gate level power reduction methods for combinational circuits by stopping unnecessary input changes of gates. In Pseudo PG, an extra control signal might be added to a gate and other input changes of the gate are deactivated when the control signal takes the controlling value. To improve the power reduction capability, the paper newly introduces dual-stage Pseudo PG with advanced clustering algorithm where up to two extra control signals are added to a gate if effective. The advanced clustering algorithm selects the first control signal to be compatible with the second control signal based on the propagation of controlling condition via a path, with which candidates of controllable gates excluded by the maximum depth constraint can be controlled. Experimental results show that the proposed dual-stage Pseudo PG method has obtained 23.23% average power reduction with 5.28% delay penalty with respect to the original circuits, and has obtained 10.46% more power reduction with 2.75% delay penalty compared with respect to circuits applying the original single-stage Pseudo PG.

Obtaining a linearizing feedback and a coordinate transformation map is very difficult, even though the system is feedback linearizable. It is known that finding a desired transformation map and feedback is equivalent to finding an integrating factor for an annihilating one-form for single input nonlinear systems. It is also known that such an integrating factor can be approximated using the simple C.I.R method and tensor product splines. In this paper, it is shown that m integrating factors can always be approximated whenever a nonlinear system with m inputs is feedback linearizable. Next, m zero-forms can be constructed by utilizing these m integrating factors and the same methodology in the single input case. Hence, the coordinate transformation map is obtained.

We develop an optimum code allocation scheme by investigating the peak to average power ratio (PAPR) characteristic of a down-link multi-carrier (MC)-CDMA system using Walsh-Hadamard code. It is shown that PAPR of a MC-CDMA system is highly dependent upon the selection of code combination. Based on this fact, we develop the allocation method which minimizes PAPR according to the number of active users. In addition, an efficient suboptimum code combination search scheme is also proposed for near minimum PAPR.