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IEICE TRANSACTIONS on Fundamentals

Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization

Yu JIN, Zhe DU, Shinji KIMURA

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Summary :

Pseudo Power Gating (Pseudo PG) is one of gate level power reduction methods for combinational circuits by stopping unnecessary input changes of gates. In Pseudo PG, an extra control signal might be added to a gate and other input changes of the gate are deactivated when the control signal takes the controlling value. To improve the power reduction capability, the paper newly introduces dual-stage Pseudo PG with advanced clustering algorithm where up to two extra control signals are added to a gate if effective. The advanced clustering algorithm selects the first control signal to be compatible with the second control signal based on the propagation of controlling condition via a path, with which candidates of controllable gates excluded by the maximum depth constraint can be controlled. Experimental results show that the proposed dual-stage Pseudo PG method has obtained 23.23% average power reduction with 5.28% delay penalty with respect to the original circuits, and has obtained 10.46% more power reduction with 2.75% delay penalty compared with respect to circuits applying the original single-stage Pseudo PG.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2568-2575
Publication Date
2013/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E96.A.2568
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Logic Synthesis, Test and Verification

Authors

Yu JIN
  Waseda University
Zhe DU
  Waseda University
Shinji KIMURA
  Waseda University

Keyword