IEICE TRANSACTIONS on Information
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
Summary :
Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.8 pp.1613-1623
- Publication Date
- 2013/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.1613
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Test and Verification
Authors
Kazuteru NAMBA
Chiba University
Nobuhide TAKASHINA
Chiba University
Hideo ITO
Chiba University
Keyword
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Kazuteru NAMBA, Nobuhide TAKASHINA, Hideo ITO, "Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 8, pp. 1613-1623, August 2013, doi: 10.1587/transinf.E96.D.1613.
Abstract: Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1613/_p
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@ARTICLE{e96-d_8_1613,
author={Kazuteru NAMBA, Nobuhide TAKASHINA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA},
year={2013},
volume={E96-D},
number={8},
pages={1613-1623},
abstract={Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.},
keywords={},
doi={10.1587/transinf.E96.D.1613},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
T2 - IEICE TRANSACTIONS on Information
SP - 1613
EP - 1623
AU - Kazuteru NAMBA
AU - Nobuhide TAKASHINA
AU - Hideo ITO
PY - 2013
DO - 10.1587/transinf.E96.D.1613
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2013
AB - Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.
ER -
English
