IEICE TRANSACTIONS on Fundamentals
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
Summary :
As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2487-2498
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2487
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Level Design
Authors
Yu ZHANG
University of Kitakyushu
Gong CHEN
University of Kitakyushu
Bo YANG
Design Algorithm Laboratory, Inc.
Jing LI
Design Algorithm Laboratory, Inc.
Qing DONG
University of Kitakyushu
Ming-Yu LI
University of Kitakyushu,Chongqing University
Shigetoshi NAKATAKE
University of Kitakyushu
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yu ZHANG, Gong CHEN, Bo YANG, Jing LI, Qing DONG, Ming-Yu LI, Shigetoshi NAKATAKE, "Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2487-2498, December 2013, doi: 10.1587/transfun.E96.A.2487.
Abstract: As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2487/_p
Copy
@ARTICLE{e96-a_12_2487,
author={Yu ZHANG, Gong CHEN, Bo YANG, Jing LI, Qing DONG, Ming-Yu LI, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming},
year={2013},
volume={E96-A},
number={12},
pages={2487-2498},
abstract={As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.},
keywords={},
doi={10.1587/transfun.E96.A.2487},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2487
EP - 2498
AU - Yu ZHANG
AU - Gong CHEN
AU - Bo YANG
AU - Jing LI
AU - Qing DONG
AU - Ming-Yu LI
AU - Shigetoshi NAKATAKE
PY - 2013
DO - 10.1587/transfun.E96.A.2487
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.
ER -
English
