A new structure of the electro-optic modulator to compensate the third-order intermodulation distortion (IMD3) is introduced. The modulator includes two Mach-Zehnder modulators (MZMs) operating with frequency chirp and the two modulated outputs are combined with an adequate phase difference. We revealed by theoretical analysis and numerical calculations that the IMD3 components in the receiver output could be selectively suppressed when the two MZMs operate with chirp parameters of opposite signs to each other. Spectral power of the IMD3 components in the proposed modulator was more than 15dB lower than that in a normal Mach-Zehnder modulator at modulation index between 0.15π and 0.25π rad. The IMD3 compensation properties of the proposed modulator was experimentally confirmed by using a dual parallel Mach-Zehnder modulator (DPMZM) structure. We designed and fabricated the modulator with the single-chip structure and the single-input operation by integrating with 180° hybrid coupler on the modulator substrate. Modulation signals were applied to each modulation electrode by the 180° hybrid coupler to set the chirp parameters of two MZMs of the DPMZM. The properties of the fabricated modulator were measured by using 10GHz two-tone signals. The performance of the IMD3 compensation agreed with that in the calculation. It was confirmed that the IMD3 compensation could be realized even by the fabricated modulator structure.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.

Matching circuits using LC elements are widely applied to high-frequency circuits such as power amplifier (PA) and low-noise amplifier (LNA). For determining matching condition of multi-stage matching circuits, this paper shows that any multi-stage LC-Ladder matching circuit with resistive termination can be decomposed to the extended L-type matching circuits with resistive termination containing negative elements where the analytical solution exists. The matching conditions of each extended L-type matching circuit are obtained easily from the termination resistances and the design frequency. By synthesizing these simple analysis solutions, it is possible to systematically determine the solution even in a large number of stages (high order) matching circuits.

An effect of complex permeability of noise suppression sheets (NSS) on circuit parameters was investigated by a magnetic circuit analysis using cross-sectional size and material parameters. The series resistance and inductance of the coplanar waveguide (CPW) with a NSS considering the effect of the complex permeability of the NSS were quantitatively estimated. The result indicated that the imaginary and real part of the effective permeability affected the resistance and inductance, respectively. Furthermore, this analysis was applied to an 8-µm-wide CPW with a 0.5-µm-thick Co85Zr3Nb12 film for quantitative estimation of the resistance, the inductance and the characteristic impedance. The estimated parameters were almost similar to the measured values. These results showed that the frequency characteristics of the circuit parameters could be controlled by changing size and material parameters.

The accurate calculation of the inductance is the most basic problem of the inductor design. In this paper, the core flux density distribution and leakage flux in core window and winding of core-type inductor are analyzed by finite element analysis (FEA) firstly. Based on it, an improved magnetic equivalent circuit with high accuracy flux density distribution (iMEC) is proposed for a single-phase core-type inductor. Depend on the geometric structure, two leakage paths of the core window are modeled. Furthermore, the iMEC divides the magnetomotive force of the winding into the corresponding core branch. It makes the core flux density distribution consistent with the FEA distribution to improve the accuracy of the inductance. In the iMEC, flux density of the core leg has an error less than 5.6% compared to FEA simulation at 150A. The maximum relative error of the inductance is less than 8.5% and the average relative error is less than 6% compared to the physical prototype test data. At the same time, due to the high computational efficiency of iMEC, it is very suitable for the population-based optimization design.

A low frequency electric field probe that integrates data acquisition and storage is developed in this paper. An electric small monopole antenna printed on the circuit board is used as the receiving antenna; the rear end of the monopole antenna is connected to the integral circuit to achieve the flat frequency response; the logarithmic detection method is applied to obtain a high measurement dynamic range. In addition, a Microprogrammed Control Unit is set inside to realize data acquisition and storage. The size of the probe developed is not exceeding 20 mm × 20 mm × 30 mm. The field strength 0.2 V/m ~ 261 V/m can be measured in the frequency range of 500 Hz ~ 10 MHz, achieving a dynamic range over 62 dB. It is suitable for low frequency electric field strength measurement and shielding effectiveness test of small shield.

A triple-band CP rectenna for ambient RF energy harvesting is presented in this paper. A simple broadband CP slot antenna has been proposed with the bandwidth of 51.1% operating from 1.53 to 2.58GHz, which can cover GSM-1800, UMTS-2100 and 2.45GHz WLAN bands. Accordingly, a triple-band rectifying circuit is designed to convert RF energy in the above bands, with the maximum RF-DC conversion efficiency of 42.5% at a relatively low input power of -5dBm. Additionally, the rectenna achieves the maximum conversion efficiency of 12.7% in the laboratory measurements. The measured results show a good performance in the laboratory measurements.

This paper presents the feasibility of a capacitive coupler utilizing an electric double layer for wireless power transfer under seawater. Since seawater is an electrolyte solution, an electric double layer (EDL) is formed on the electrode surface of the coupler in direct current. If the EDL can be utilized in radio frequency, it is possible that high power transfer efficiency can be achieved under seawater because a high Q-factor can be obtained. To clarify this, the following steps need taking; First, measure the frequency characteristics of the complex permittivity in seawater and elucidate the behaviors of the EDL from the results. Second, clarify that EDL leads to an improvement in the Q-factor of seawater. It will be shown in this paper that capacitive coupling by EDL occurs using two kinds of the coupler models. Third, design a coupler with high efficiency as measured by the Q-factor and relative permittivity of EDL. Last, demonstrate that the designed coupler under seawater can achieve over 85% efficiency at a transfer distance of 5 mm and feasibility of the coupler with EDL.

In this paper, experimental data of non-arcing circuit breaking phenomena in electrical contacts are presented. A dark bridge that is a non-luminous bridge between electrical contacts is an effective factor for the non-arcing circuit break. A facility of a cantilever system was established to precisely control a position of an electrode. By using this facility, dark bridges between contacts were made and the dark bridges were observed by a microscopic camera system.

This paper presents the excitation coefficient optimization of slot array antennas for increasing channel capacity in 2×2-mode two-dimensional ROM (rectangular coordinate orthogonal) transmission. Because the ROM transmission is for non-far region communication, the transmission between Tx (transmission) and Rx (reception) antennas increases when the antennas radiate beams inwardly. At first, we design the excitation coefficients of the slot arrays in order to enhance the transmission rate for a given transmission distance. Then, we fabricate monopulse corporate-feed waveguide slot array antennas that have the designed excitation amplitude and phase in the 60-GHz band for the 2×2-mode two-dimensional ROM transmission. The measured transmission between the fabricated Tx and Rx antennas increases at the given propagation distance and agrees with the simulation.

In this letter, an active complex filter with finite transmission zeros is proposed. In order to obtain a complex prototype ladder filter including no inductors, a new circuit transformation is proposed. This circuit is classified into the RiCR filter. It is shown that it includes no negative capacitors when it is obtained through a frequency transformation. The validity of the proposed method is confirmed through computer simulation.

Register-transfer-level (RTL) information is hardly available for hardware Trojan detection. In this paper, four RTL Trojan features related to branching statement are proposed. The Minimum Redundancy Maximum Relevance (mRMR) feature selection is applied to the proposed Trojan features to determine the recommended feature combinations. The feature combinations are then tested using different machine learning concepts in order to determine the best approach for classifying Trojan and normal branches. The result shows that a Decision Tree classification algorithm with all the four proposed Trojan features can achieve an average true positive detection rate of 93.72% on unseen test data.

Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.

To implement the parallel acceleration of convolution operation of Convolutional Neural Networks (CNNs) on field programmable gate array (FPGA), large quantities of the logic resources will be consumed, expecially DSP cores. Many previous researches fail to make a well balance between DSP and LUT6. For better resource efficiency, a typical convolution structure is implemented with LUT6s in this paper. Besides, a novel convolution structure is proposed to further reduce the LUT6 resource consumption by modifying the typical convolution structure. The equations to evaluate the LUT6 resource consumptions of both structures are presented and validated. The theoretical evaluation and experimental results show that the novel structure can save 3.5-8% of LUT6s compared with the typical structure.

This paper introduces methods to modify a buggy sequential gate-level circuit to conform to the specification. In order to preserve the optimization efforts, the modifications should be as small as possible. Assuming that the locations to be modified are given, our proposed method finds an appropriate set of fan-in signals for the patch function of those locations by iteratively calculating the state correspondence between the specification and the buggy circuit and applying a method for debugging combinational circuits. The experiments are conducted on ITC99 benchmark circuits, and it is shown that our proposed method can work when there are at most 30,000 corresponding reachable state pairs between two circuits. Moreover, a heuristic method using the information of data-path FFs is proposed, which can find a correct set of fan-ins for all the benchmark circuits within practical time.

Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.

In order to obtain high-performance circuits in advanced technology nodes, design methodology has to take the existence of large delay variations into account. Clock scheduling and speculative execution have overheads to realize them, but have potential to improve the performance by averaging the imbalance of maximum delay among paths and by utilizing valid data available earlier than worst-case scenarios, respectively. In this paper, we propose a high-performance digital circuit design method with speculative executions with less overhead by utilizing clock scheduling with delay insertions effectively. The necessity of speculations that cause overheads is effectively reduced by clock scheduling with delay insertion. Experiments show that a generated circuit achieves 26% performance improvement with 1.3% area overhead compared to a circuit without clock scheduling and without speculative execution.

In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.

In full duplex (FD), which improves the system capacity (or cell throughput) and reduces the transmission delay (or latency) through simultaneous transmission and reception in the same frequency band, self-interference (SI) from the transmitter should be suppressed using antenna isolation, an analog SI canceler, and digital SI canceler (DSIC) to a level such that the data or control channel satisfies the required block error rate (BLER). This paper proposes a structure of iterative DSIC with alternating estimate subtraction (AES-IDSIC) for orthogonal frequency division multiplexing (OFDM) using FD. We first present the required SI suppression level considering SI, quantization noise of an analog-to-digital converter, and nonlinear distortion of a power amplifier and RF receiver circuit for a direct conversion transceiver using FD. Then, we propose an AES-IDSIC structure that iterates the generation of the SI estimate, the downlink symbol estimate, and then alternately removes one of the estimates from the received signal in the downlink including SI. We investigate the average BLER performance of the AES-IDSIC for OFDM using FD in a multipath fading channel based on link-level simulations under the constraint that the derived required signal-to-SI ratio must be satisfied.

In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.