IEICE TRANSACTIONS on Fundamentals
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
Summary :
Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.12 pp.1751-1759
- Publication Date
- 2019/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.1751
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Ryosuke MATSUO
Kyoto University
Jun SHIOMI
Kyoto University
Tohru ISHIHARA
Kyoto University
Hidetoshi ONODERA
Kyoto University
Akihiko SHINYA
NTT Corporation
Masaya NOTOMI
NTT Corporation
Keyword
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Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, "Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1751-1759, December 2019, doi: 10.1587/transfun.E102.A.1751.
Abstract: Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1751/_p
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@ARTICLE{e102-a_12_1751,
author={Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits},
year={2019},
volume={E102-A},
number={12},
pages={1751-1759},
abstract={Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.},
keywords={},
doi={10.1587/transfun.E102.A.1751},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1751
EP - 1759
AU - Ryosuke MATSUO
AU - Jun SHIOMI
AU - Tohru ISHIHARA
AU - Hidetoshi ONODERA
AU - Akihiko SHINYA
AU - Masaya NOTOMI
PY - 2019
DO - 10.1587/transfun.E102.A.1751
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.
ER -
English
