IEICE TRANSACTIONS on Communications
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Summary :
Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E103-B No.1 pp.11-19
- Publication Date
- 2020/01/01
- Publicized
- 2019/08/05
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.2019CPP0001
- Type of Manuscript
- Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
- Category
- Network System
Authors
Yuta UKON
NTT Corporation
Koji YAMAZAKI
NTT Corporation
Koyo NITTA
NTT Corporation
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yuta UKON, Koji YAMAZAKI, Koyo NITTA, "Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture" in IEICE TRANSACTIONS on Communications,
vol. E103-B, no. 1, pp. 11-19, January 2020, doi: 10.1587/transcom.2019CPP0001.
Abstract: Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2019CPP0001/_p
Copy
@ARTICLE{e103-b_1_11,
author={Yuta UKON, Koji YAMAZAKI, Koyo NITTA, },
journal={IEICE TRANSACTIONS on Communications},
title={Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture},
year={2020},
volume={E103-B},
number={1},
pages={11-19},
abstract={Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.},
keywords={},
doi={10.1587/transcom.2019CPP0001},
ISSN={1745-1345},
month={January},}
Copy
TY - JOUR
TI - Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
T2 - IEICE TRANSACTIONS on Communications
SP - 11
EP - 19
AU - Yuta UKON
AU - Koji YAMAZAKI
AU - Koyo NITTA
PY - 2020
DO - 10.1587/transcom.2019CPP0001
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E103-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 2020
AB - Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
ER -
English
