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IEICE TRANSACTIONS on Information

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks

Kota ANDO, Kodai UEYOSHI, Yuka OBA, Kazutoshi HIROSE, Ryota UEMATSU, Takumi KUDO, Masayuki IKEBE, Tetsuya ASAI, Shinya TAKAMAEDA-YAMAZAKI, Masato MOTOMURA

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Summary :

Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.

Publication
IEICE TRANSACTIONS on Information Vol.E102-D No.12 pp.2341-2353
Publication Date
2019/12/01
Publicized
2019/07/22
Online ISSN
1745-1361
DOI
10.1587/transinf.2019PAP0009
Type of Manuscript
Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category
Computer System

Authors

Kota ANDO
  Tokyo Institute of Technology
Kodai UEYOSHI
  Hokkaido University
Yuka OBA
  Hokkaido University
Kazutoshi HIROSE
  Hokkaido University
Ryota UEMATSU
  Hokkaido University
Takumi KUDO
  Hokkaido University
Masayuki IKEBE
  Hokkaido University
Tetsuya ASAI
  Hokkaido University
Shinya TAKAMAEDA-YAMAZAKI
  The University of Tokyo,JST PRESTO
Masato MOTOMURA
  Tokyo Institute of Technology

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