Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.
Kota ANDO
Tokyo Institute of Technology
Kodai UEYOSHI
Hokkaido University
Yuka OBA
Hokkaido University
Kazutoshi HIROSE
Hokkaido University
Ryota UEMATSU
Hokkaido University
Takumi KUDO
Hokkaido University
Masayuki IKEBE
Hokkaido University
Tetsuya ASAI
Hokkaido University
Shinya TAKAMAEDA-YAMAZAKI
The University of Tokyo,JST PRESTO
Masato MOTOMURA
Tokyo Institute of Technology
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Kota ANDO, Kodai UEYOSHI, Yuka OBA, Kazutoshi HIROSE, Ryota UEMATSU, Takumi KUDO, Masayuki IKEBE, Tetsuya ASAI, Shinya TAKAMAEDA-YAMAZAKI, Masato MOTOMURA, "Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 12, pp. 2341-2353, December 2019, doi: 10.1587/transinf.2019PAP0009.
Abstract: Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2019PAP0009/_p
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@ARTICLE{e102-d_12_2341,
author={Kota ANDO, Kodai UEYOSHI, Yuka OBA, Kazutoshi HIROSE, Ryota UEMATSU, Takumi KUDO, Masayuki IKEBE, Tetsuya ASAI, Shinya TAKAMAEDA-YAMAZAKI, Masato MOTOMURA, },
journal={IEICE TRANSACTIONS on Information},
title={Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks},
year={2019},
volume={E102-D},
number={12},
pages={2341-2353},
abstract={Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.},
keywords={},
doi={10.1587/transinf.2019PAP0009},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
T2 - IEICE TRANSACTIONS on Information
SP - 2341
EP - 2353
AU - Kota ANDO
AU - Kodai UEYOSHI
AU - Yuka OBA
AU - Kazutoshi HIROSE
AU - Ryota UEMATSU
AU - Takumi KUDO
AU - Masayuki IKEBE
AU - Tetsuya ASAI
AU - Shinya TAKAMAEDA-YAMAZAKI
AU - Masato MOTOMURA
PY - 2019
DO - 10.1587/transinf.2019PAP0009
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2019
AB - Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.
ER -