We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO2. For both OFET types, the Vth can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO2. The stability of the shifted Vth was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 106 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage VDD, leading to the maximum electrical noise immunity of the inverter circuit.
Toan Thanh DAO
University of Transport and Communications
Hideyuki MURATA
Japan Advanced Institute of Science and Technology
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Toan Thanh DAO, Hideyuki MURATA, "Tunable Threshold Voltage of Organic CMOS Inverter Circuits by Electron Trapping in Bilayer Gate Dielectrics" in IEICE TRANSACTIONS on Electronics,
vol. E98-C, no. 5, pp. 422-428, May 2015, doi: 10.1587/transele.E98.C.422.
Abstract: We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO2. For both OFET types, the Vth can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO2. The stability of the shifted Vth was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 106 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage VDD, leading to the maximum electrical noise immunity of the inverter circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.422/_p
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@ARTICLE{e98-c_5_422,
author={Toan Thanh DAO, Hideyuki MURATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Tunable Threshold Voltage of Organic CMOS Inverter Circuits by Electron Trapping in Bilayer Gate Dielectrics},
year={2015},
volume={E98-C},
number={5},
pages={422-428},
abstract={We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO2. For both OFET types, the Vth can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO2. The stability of the shifted Vth was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 106 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage VDD, leading to the maximum electrical noise immunity of the inverter circuit.},
keywords={},
doi={10.1587/transele.E98.C.422},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Tunable Threshold Voltage of Organic CMOS Inverter Circuits by Electron Trapping in Bilayer Gate Dielectrics
T2 - IEICE TRANSACTIONS on Electronics
SP - 422
EP - 428
AU - Toan Thanh DAO
AU - Hideyuki MURATA
PY - 2015
DO - 10.1587/transele.E98.C.422
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2015
AB - We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO2. For both OFET types, the Vth can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO2. The stability of the shifted Vth was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 106 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage VDD, leading to the maximum electrical noise immunity of the inverter circuit.
ER -