Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

A new graphic and display processor, which is suitable for high-performance car navigation systems or next-generation ITS mobile terminals, has been developed. The performance bottleneck of conventional consumer graphic systems exists not only in the rendering performance of the graphic processor itself, but also in CPU-capability and CPU-bus bandwidth. To release this latter bottleneck, the new processor has Controller/DSP Unit and FPU for graphic-macro-command parsing and geometric operations, respectively, which used to be the CPU tasks and occupy some amount of CPU-bus bandwidth to transfer their results. The architecture of the new processor is organized so as to carry out macro-pipelined operations of graphic and display processing smoothly. One of the features of this processor is having special hardware, Polygon-Engine and Short-Vector-Accelerator, for the rapid rendering of 2D maps, where complex polygons and short line-segments are the dominant objects to be rendered. Another feature is the hardware support of multi-layer/window display with alpha-blend overlapping. This function and additional video processing capability, such as MPEG4 decoding, would be useful in the next generation intelligent terminals. The processor LSI has been successfully fabricated by using 0.18 µm standard CMOS technology. More than five million transistors are implemented on this chip. The peak rendering speed of this processor has been measured as 200 Mpixel/s at 133 MHz processor internal clock frequency. Other results of the graphic system evaluation have demonstrated that this new processor has appropriately high performance and useful functions for the next generation mobile terminals.

We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.