A new graphic and display processor, which is suitable for high-performance car navigation systems or next-generation ITS mobile terminals, has been developed. The performance bottleneck of conventional consumer graphic systems exists not only in the rendering performance of the graphic processor itself, but also in CPU-capability and CPU-bus bandwidth. To release this latter bottleneck, the new processor has Controller/DSP Unit and FPU for graphic-macro-command parsing and geometric operations, respectively, which used to be the CPU tasks and occupy some amount of CPU-bus bandwidth to transfer their results. The architecture of the new processor is organized so as to carry out macro-pipelined operations of graphic and display processing smoothly. One of the features of this processor is having special hardware, Polygon-Engine and Short-Vector-Accelerator, for the rapid rendering of 2D maps, where complex polygons and short line-segments are the dominant objects to be rendered. Another feature is the hardware support of multi-layer/window display with alpha-blend overlapping. This function and additional video processing capability, such as MPEG4 decoding, would be useful in the next generation intelligent terminals. The processor LSI has been successfully fabricated by using 0.18 µm standard CMOS technology. More than five million transistors are implemented on this chip. The peak rendering speed of this processor has been measured as 200 Mpixel/s at 133 MHz processor internal clock frequency. Other results of the graphic system evaluation have demonstrated that this new processor has appropriately high performance and useful functions for the next generation mobile terminals.