High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM

Toshikazu SUZUKI; Toru IWATA; Hironori AKAMATSU; Akihiro SAWADA; Toshiaki TSUJI; Hiroyuki YAMAUCHI; Takashi TANIGUCHI; Tsutomu FUJITA

High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM

Toshikazu SUZUKI, Toru IWATA, Hironori AKAMATSU, Akihiro SAWADA, Toshiaki TSUJI, Hiroyuki YAMAUCHI, Takashi TANIGUCHI, Tsutomu FUJITA

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Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc3.3 V, and also even at V_cc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1334-1342

Publication Date: 1994/08/25

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Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)

Category: DRAM

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Toshikazu SUZUKI, Toru IWATA, Hironori AKAMATSU, Akihiro SAWADA, Toshiaki TSUJI, Hiroyuki YAMAUCHI, Takashi TANIGUCHI, Tsutomu FUJITA, "High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 8, pp. 1334-1342, August 1994, doi: .
Abstract: Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc3.3 V, and also even at V_cc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1334/_p

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@ARTICLE{e77-c_8_1334,
author={Toshikazu SUZUKI, Toru IWATA, Hironori AKAMATSU, Akihiro SAWADA, Toshiaki TSUJI, Hiroyuki YAMAUCHI, Takashi TANIGUCHI, Tsutomu FUJITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM},
year={1994},
volume={E77-C},
number={8},
pages={1334-1342},
abstract={Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc3.3 V, and also even at V_cc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 1334
EP - 1342
AU - Toshikazu SUZUKI
AU - Toru IWATA
AU - Hironori AKAMATSU
AU - Akihiro SAWADA
AU - Toshiaki TSUJI
AU - Hiroyuki YAMAUCHI
AU - Takashi TANIGUCHI
AU - Tsutomu FUJITA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc3.3 V, and also even at V_cc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.
ER -