We improve the cycle time performance of EtherCAT networks with embedded Linux-based master by developing a Linux Ethernet driver optimized for EtherCAT operation. The Ethernet driver is developed to establish a direct interface between the master module and Ethernet controllers of embedded systems by removing the involvement of Linux network stack and the New API (NAPI) of standard Ethernet drivers. Consequently, it is achieved that the time-consuming memory copy operations are reduced and the process of EtherCAT frames is accelerated. In order to demonstrate the effect of the developed Ethernet driver, we set up EtherCAT networks composed of an embedded Linux-based master and commercial off-the-shelf slaves, and the experimental results confirm that the cycle time performance is significantly improved.

This paper presents a new cycle time synchronization method to transmit isochronous multimedia data by real time in IEEE 1394 over a UWB (ultra wide-band) network. The 1394 TA recommended two methods for the cycle time synchronization. The first method must use two consecutive beacon signals to calculate a drift correction, while the second one eliminates this dependency with minor algorithm changes. As experimental results, the second method achieves 21% performance improvement over the first one. The receipt of two consecutive beacons every time is hard due to the noise in a wireless channel. In addition, this paper provides the procedure of cycle time synchronization, as well as the transaction between 1394 protocol adaptation layer and IEEE 802.15.3 media access layer. The proposed synchronization technique will contribute to transfer isochronous data at IEEE 1394 over UWB audio/visual appliances such as camcorder, HDTV, etc.

A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm2 chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm2). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.