We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits
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Shigeo KUNINOBU, Tamotsu NISHIYAMA, Takashi TANIGUCHI, "High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 3, pp. 436-445, March 1993, doi: .
Abstract: We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_3_436/_p
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@ARTICLE{e76-c_3_436,
author={Shigeo KUNINOBU, Tamotsu NISHIYAMA, Takashi TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor},
year={1993},
volume={E76-C},
number={3},
pages={436-445},
abstract={We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 436
EP - 445
AU - Shigeo KUNINOBU
AU - Tamotsu NISHIYAMA
AU - Takashi TANIGUCHI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1993
AB - We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits
ER -