A 4096-channel time-switch LSI with switching address protection is described. To achieve the large switching capacity, a double buffer architecture was adopted, and divided cell array structures were implemented using an automatic layout method. A 4096 w 1 b protection memory is included in the control memory to avoid snappings of paths through fixed switching addresses. The memory area and design complexity were reduced by developing a new method for constructing a memory array with variable capacities and multiple-WE (Write-Enable Signal) control systems. The chip was fabricated with 0.8 µm BiCMOS technology and operates at over 32 Mb/s with a power consumption of 1.2 W.

This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.