High-Speed Time Division Switch Operating at 256 Mb/s

Naoaki YAMANAKA; Masaharu KAWAKAMI; Yasukazu TERADA

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Naoaki YAMANAKA, Masaharu KAWAKAMI, Yasukazu TERADA, "High-Speed Time Division Switch Operating at 256 Mb/s" in IEICE TRANSACTIONS on transactions, vol. E68-E, no. 9, pp. 570-571, September 1985, doi: .
Abstract: This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e68-e_9_570/_p

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@ARTICLE{e68-e_9_570,
author={Naoaki YAMANAKA, Masaharu KAWAKAMI, Yasukazu TERADA, },
journal={IEICE TRANSACTIONS on transactions},
title={High-Speed Time Division Switch Operating at 256 Mb/s},
year={1985},
volume={E68-E},
number={9},
pages={570-571},
abstract={This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - High-Speed Time Division Switch Operating at 256 Mb/s
T2 - IEICE TRANSACTIONS on transactions
SP - 570
EP - 571
AU - Naoaki YAMANAKA
AU - Masaharu KAWAKAMI
AU - Yasukazu TERADA
PY - 1985
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E68-E
IS - 9
JA - IEICE TRANSACTIONS on transactions
Y1 - September 1985
AB - This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.
ER -