Design of High-Radix VLSI Dividers without Quotient Selection Tables
Summary :
In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2623-2631
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Design
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Takafumi AOKI, Kimihiko NAKAZAWA, Tatsuo HIGUCHI, "Design of High-Radix VLSI Dividers without Quotient Selection Tables" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2623-2631, November 2001, doi: .
Abstract: In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2623/_p
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@ARTICLE{e84-a_11_2623,
author={Takafumi AOKI, Kimihiko NAKAZAWA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of High-Radix VLSI Dividers without Quotient Selection Tables},
year={2001},
volume={E84-A},
number={11},
pages={2623-2631},
abstract={In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Design of High-Radix VLSI Dividers without Quotient Selection Tables
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2623
EP - 2631
AU - Takafumi AOKI
AU - Kimihiko NAKAZAWA
AU - Tatsuo HIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.
ER -
English
