IEICE TRANSACTIONS on transactions
A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier
Summary :
This paper proposes a new residue number multiplication scheme based on the cylic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E68-E No.1 pp.14-21
- Publication Date
- 1985/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Signal Processing
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Keyword
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Michitaka KAMEYAMA, Oluwole ADEGBENRO, Tatsuo HIGUCHI, "A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier" in IEICE TRANSACTIONS on transactions,
vol. E68-E, no. 1, pp. 14-21, January 1985, doi: .
Abstract: This paper proposes a new residue number multiplication scheme based on the cylic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e68-e_1_14/_p
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@ARTICLE{e68-e_1_14,
author={Michitaka KAMEYAMA, Oluwole ADEGBENRO, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on transactions},
title={A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier},
year={1985},
volume={E68-E},
number={1},
pages={14-21},
abstract={This paper proposes a new residue number multiplication scheme based on the cylic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.},
keywords={},
doi={},
ISSN={},
month={January},}
Copy
TY - JOUR
TI - A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier
T2 - IEICE TRANSACTIONS on transactions
SP - 14
EP - 21
AU - Michitaka KAMEYAMA
AU - Oluwole ADEGBENRO
AU - Tatsuo HIGUCHI
PY - 1985
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E68-E
IS - 1
JA - IEICE TRANSACTIONS on transactions
Y1 - January 1985
AB - This paper proposes a new residue number multiplication scheme based on the cylic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.
ER -
English
