IEICE TRANSACTIONS on Fundamentals
A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS
Summary :
High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.11 pp.1907-1914
- Publication Date
- 2018/11/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.1907
- Type of Manuscript
- PAPER
- Category
- Circuit Theory
Authors
Masahiro ICHIHASHI
Kyushu University
Haruichi KANAYA
Kyushu University
Keyword
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Masahiro ICHIHASHI, Haruichi KANAYA, "A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 11, pp. 1907-1914, November 2018, doi: 10.1587/transfun.E101.A.1907.
Abstract: High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.1907/_p
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@ARTICLE{e101-a_11_1907,
author={Masahiro ICHIHASHI, Haruichi KANAYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS},
year={2018},
volume={E101-A},
number={11},
pages={1907-1914},
abstract={High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.},
keywords={},
doi={10.1587/transfun.E101.A.1907},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1907
EP - 1914
AU - Masahiro ICHIHASHI
AU - Haruichi KANAYA
PY - 2018
DO - 10.1587/transfun.E101.A.1907
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2018
AB - High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.
ER -
English
