IEICE TRANSACTIONS on Electronics
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
Summary :
A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.7 pp.1142-1150
- Publication Date
- 2008/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.7.1142
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
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Kenta YAMADA, Takashi SATO, Shuhei AMAKAWA, Noriaki NAKAYAMA, Kazuya MASU, Shigetaka KUMASHIRO, "Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 7, pp. 1142-1150, July 2008, doi: 10.1093/ietele/e91-c.7.1142.
Abstract: A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.7.1142/_p
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@ARTICLE{e91-c_7_1142,
author={Kenta YAMADA, Takashi SATO, Shuhei AMAKAWA, Noriaki NAKAYAMA, Kazuya MASU, Shigetaka KUMASHIRO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress},
year={2008},
volume={E91-C},
number={7},
pages={1142-1150},
abstract={A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to
keywords={},
doi={10.1093/ietele/e91-c.7.1142},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
T2 - IEICE TRANSACTIONS on Electronics
SP - 1142
EP - 1150
AU - Kenta YAMADA
AU - Takashi SATO
AU - Shuhei AMAKAWA
AU - Noriaki NAKAYAMA
AU - Kazuya MASU
AU - Shigetaka KUMASHIRO
PY - 2008
DO - 10.1093/ietele/e91-c.7.1142
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2008
AB - A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to
ER -
English
