A method for estimating circuit performance variation caused by packaging-induced mechanical stress is proposed. The developed method is based on the stress distribution chart for the target integrated circuit (IC) and the stress sensitivity characteristics of individual devices. This information is experimentally obtained using a specially designed test chip and a cantilever bending calibration system. A post-packaging analysis and simulation tool, called Stress Netlist Generator (SNG), is developed for conducting the proposed method. Based on the stress distribution chart and the stress sensitivity characteristics, SNG modifies the SPICE model parameters in the target netlist according to the impact of the packaging-induced stress. The netlist generated by SNG is used to estimate packaging-induced performance variation with high accuracy. The developed method is remarkably effective even for small-scale ICs with chip sizes of roughly 1 mm2, such as power management ICs, which require higher precision.

Fast simulation techniques of large scale RLC networks with nonlinear devices are presented. Generally, when scale of nonlinear part in a circuit is much less than the linear part, matrix or circuit partitioning approach is known to be efficient. In this paper, these partitioning techniques are used for the conventional transient analysis using an implicit numerical integration and the circuit-based finite-difference time-domain (FDTD) method, whose efficiency and accuracy are evaluated developing a prototype simulator. It is confirmed that the matrix and circuit partitioning approaches do not degrade accuracy of the transient simulations that is compatible to SPICE, and that the circuit partitioning approach is superior to the matrix one in efficiency. Moreover, it is demonstrated that the circuit-based FDTD method can be efficiently combined with the matrix or circuit partitioning approach, compared with the transient analysis using an implicit numerical integration.

We have improved a compact model for the injection-enhancedinsulated-gate bipolar transistor for inverter circuit simulation. The holeaccumulation of floating-base region and potential change are modeled. It turned out that negative capacitance which occurs by floating-base region has the dependence of frequency. It is necessary to consider the frequency dependence of the total gate capacitance for transient simulation. We analyzed the relationship between negative gate capacitance and current rise rate at the switch turn-on timing and device structure. The development model simulation result is well reproduced $I_{ extrm{c}}$ and $V_{ extrm{ce}}$ of measurement data, and the switching loss calculation accuracy is improved.

Homotopy methods are known to be effective methods for finding DC operating points of nonlinear circuits with the theoretical guarantee of global convergence. There are several types of homotopy methods; as one of the most efficient methods for solving bipolar transistor circuits, the variable-gain homotopy (VGH) method is well-known. In this paper, we propose an efficient VGH method for solving bipolar and MOS transistor circuits. We also show that the proposed method converges to a stable operating point with high possibility from any initial point. The proposed method is not only globally convergent but also more efficient than the conventional VGH methods. Moreover, it can easily be implemented in SPICE.

In this work, a measurement-based procedure aimed at deriving a behavioral model of Bulk Current Injection (BCI) probes clamped onto multi-wire cable bundles is proposed. The procedure utilizes the measurement data obtained by mounting the probe onto the calibration jig for model-parameters extraction, and 2D electromagnetic simulations to adapt such parameters to the specific characteristics of the cable bundle under analysis. Outcome of the analysis is a behavioral model which can be easily implemented into the SPICE environment. Without loss of generality, the proposed model is here used to predict the radio-frequency noise stressing the terminal units of a two-wire harness. Model accuracy in predicting the common and differential mode voltages induced by BCI at the line terminals is assessed by EM modeling and simulation of the involved injection setup by the commercial software CST Microwave Studio.

Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.

Reverse-recovery modeling for p-i-n diodes in the high current-density conditions are discussed. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained in the high current-density conditions, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. In addition, a specific feature under the high current-density condition is discussed. The proposed model is implemented into a commercial circuit simulator in the Verilog-A language and its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.

We derive physics-based formula of current-voltage characteristic for resonant tunneling diodes (RTDs) by using the Voigt function. The Voigt function describes the mixing condition of homogeneous and inhomogeneous broadenings of peak energy width in transmission probability, which is sensitively reflected to nonlinear negative differential resistance of RTDs. The obtained formula is applicable to the SPICE model of RTD without performing numerical integrals. We indicate validity of the formula by comparing to measured data for double-barrier and triple-barrier RTDs.

This paper introduces a new technique for electromagnetic immunity modeling of integrated circuits (ICs), compliant with industrial requirements and valid up to 3 GHz. A specific modeling flow is introduced, which makes it possible to predict the conducted immunity of an IC according to a given criterion, whatever its external environment. This methodology was validated through measurements performed on several devices.

This paper provides an investigation of power distribution network (PDN) performance by a full-wave prediction tool and by experimental measurements. A set of six real boards characterized by increasing complexity is considered in order to establish a solid base for behaviour understanding of printed circuit boards. How the growing complexity impacts on the board performance is investigated by measurements and by simulations. Strengths and weakness of PDN modeling by the full-wave software tool Microwave Studio are highlighted and discussed.

Memristor is drawing more and more attraction nowadays after HP Laboratory announced its invention. Since then many researchers are taking efforts to find its applications in various areas of the information technology. Among the important applications, one of the interesting issues is the research on memristor circuits. To put forward such research, there is an urgent demand to establish a memristor SPICE model, such that people could conduct SPICE simulation to obtain the performance of the memristor circuits under their investigation. This paper reports our efforts to meet the urgent demand. Based on the memristor device fabrication technology parameters, as well as the theoretical description on memristor, we first propose memristor SPICE models, then verify the effectiveness of the proposed models by applying it to some memristor circuits. Simulation results are satisfactory.

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.

We propose here a fully Spice-oriented design algorithm of op-amps for attaining the maximum gains under low power consumptions and assigned slew-rates. Our optimization algorithm is based on a well-known steepest descent method combining with nonlinear programming. The algorithm is realized by equivalent RC circuits with ABMs (analog behavior models) of Spice. The gradient direction is decided by the analysis of sensitivity circuits. The optimum parameters can be found at the equilibrium point in the transient response of the RC circuit. Although the optimization time is much faster than the other design tools, the results might be rough because of the simple transistor models. If much better parameter values are required, they can be improved with Spice simulator and/or other tools.

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to 20% and 50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

This paper investigates the design curves of the class DE amplifier with the nonlinear shunt capacitances for any output Q and any grading coefficient m of the diode junction in the MOSFET. The design curves are derived by the numerical calculation using Spice. The results of this paper have two important meanings. Firstly, it is clarified that the nonlinearities of the shunt capacitances affect the design curves of the class DE amplifier, especially, for low output Q. Moreover, the supply voltage is a quite important parameter to design the class DE amplifier with the nonlinear shunt capacitances. Secondly, it is also clarified that the numerical design tool using Spice, which is proposed by authors, can be applied to the derivation of the design curves. This shows the possibility of the algorithm to be a powerful tool for the analysis of the class E switching circuits. The waveforms from Spice simulations denote the validity of the design curves.

The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

As a powerful computational test for nonexistence of a DC solution of a nonlinear circuit, the LP test is well-known. This test is useful for finding all solutions of nonlinear circuits; it is also useful for verifying the nonexistence of a DC operating point in a given region where operating points should not exist. However, the LP test has not been widely used in practical circuit simulation because the programming is not easy for non-experts or beginners. In this paper, we propose a new LP test that can be easily implemented on SPICE without programming. The proposed test is useful because we can easily check the nonexistence of a solution using SPICE only.

The latest LSIs still lack performance in pattern matching and picture recognition. Living organisms, on the other hand, devote very little energy to processing of this type, suggesting that they operate according to a fundamentally different concept. There is a notable difference between the two types of processing: the most similar pattern is always chosen by the conventional digital pattern matching process, whereas the choice made by an organism is not always the same: both the most similar patterns and other similar patterns are also chosen stochastically. To realize processing of this latter type, we examined a calculation method for stochastically selecting memorized patterns that show greater similar to the input pattern. Specifically, by the use of a random voltage sequence, we executed stochastic calculation and examined to what extent the accuracy of the solution is improved by increasing the number of random voltage sequences. Although calculation of the Manhattan distance cannot be realized by simply applying stochastic computing, it can be done stochastically by inputting the same random voltage sequence to two modules synchronously. We also found that the accuracy of the solution is improved by increasing the number of random voltage sequences. This processor operates so efficiently that the power consumption for calculation does not increase in proportion to the number of memorized vector elements. This characteristic is equivalent to a higher accuracy being obtained by a smaller number of random voltage sequences: a very promising characteristic of a stochastic associative processor.

Distortion analysis of nonlinear circuits is very important for designing analog integrated circuits and communication systems. In this letter, we propose an efficient frequency-domain approach for calculating frequency response curves, which is based on HB (harmonic balance) method combining with ABMs (Analog Behavior Models) of Spice. Firstly, nonlinear devices such as bipolar transistors and MOSFETs are transformed into the HB device modules executing the Fourier transformations. Using these modules, the determining equation of the HB method is formed by the equivalent sine-cosine circuit in the schematic form or net-list. It consists of the coupled resistive circuits, so that it can be efficiently solved by the DC analysis of Spice. In our algorithm, we need not to derive any troublesome circuit equations, and any kinds of the transformations.

Recently, an efficient homotopy method termed the variable gain Newton homotopy (VGNH) method has been proposed for finding DC operating points of nonlinear circuits. This method is not only very efficient but also globally convergent for any initial point. However, the programming of sophisticated homotopy methods is often difficult for non-experts or beginners. In this paper, we propose an effective method for implementing the VGNH method on SPICE. By this method, we can implement a "sophisticated VGNH method with various efficient techniques" "easily" "without programming," "although we do not know the homotopy method well."