C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.

This letter describes a method that characterizes and improves the performance of a time-interleaved (TI) digital-to-analog converter (DAC) system by using multiport signal-flow graphs at microwave frequencies. A commercial signal generator with two TI DACs was characterized through s-parameter measurements and was compared to the conventional method. Moreover, prefilters were applied to correct the response, resulting in an error-vector magnitude improvement of greater than 8 dB for a 64-quadrature-amplitude-modulated signal of 4.8 Gbps. As a result, the bandwidth limitation and the complex post processing of the conventional method could be minimized.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a current-steering digital-to-analog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and non-symmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For non-symmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed non-symmetric switching schemes are less than 64% of conventional switching schemes.

A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1 V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 µW and 0.126 mm2, respectively. The FoM is 47 fJ/conversion-step.

This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.

We propose a polarization-multiplexing QPSK modulator for synthesis of a 16 QAM signal. The generation mechanism of 16 QAM is based on an electro-optic vector digital-to-analog converter, which can generate optical multilevel signals from binary electric data sequences. A quad-parallel Mach-Zehnder modulator (QPMZM) used in our previous research requires precise control of electric signals or fabrication of a variable optical attenuator, which significantly raises the degree of difficulty to control electric signals or device fabrication. To overcome this difficulty, we developed the polarization-multiplexing QPSK modulator, which improved the method of superposition of QPSK signals. In the polarization-multiplexing QPSK modulator, two QPSK signals are output with orthogonal polarization and superposed through a polarizer. The amplitude ratio between the two QPSK signals can be precisely controlled by rotating the polarizer to arrange the 16 symbols equally. Generation of 16 QAM with 40 Gb/s and a bit error rate of 5.6910-5 was successfully demonstrated using the polarization-multiplexing QPSK modulator. This modulator has simpler configuration than the previous one, utilized a dual-polarization MZM, alleviating complicated control of electric signals.

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10 dB improvement of THD+N performance under -50 dB amplitude input signal, compared to the case without the proposed technique.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

This paper studies encoding/decoding function of artificial spiking neurons. First, we investigate basic characteristics of spike-trains of the neurons and fix parameter value that can minimize variation of spike-train length for initial value. Second we consider analog-to-digital encoding based upon spike-interval modulation that is suitable for simple and stable signal detection. Third we present a digital-to-analog decoder in which digital input is applied to switch the base signal of the spiking neuron. The system dynamics can be simplified into simple switched dynamical systems and precise analysis is possible. A simple circuit model is also presented.

A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs.

This letter considers relationship between cyclic digital-to-analog converters (DACs) and iterated function systems (IFSs). We introduce the cyclic DACs as inverse systems of analog-to-digital converters in terms of one-dimensional maps. We then compare the DACs with a typical example of existing applications of IFSs: chaos game representation for analysis of DNA structures. We also present a simple test circuit of a DAC for Gray decoding based on switched capacitors and confirm the basic operation experimentally.