IEICE TRANSACTIONS on Electronics
A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers
Summary :
This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.877-884
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.877
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Wei CHEN, Johan BAUWELINCK, Peter OSSIEUR, Xing-Zhi QIU, Jan VANDEWEGE, "A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 877-884, April 2007, doi: 10.1093/ietele/e90-c.4.877.
Abstract: This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.877/_p
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@ARTICLE{e90-c_4_877,
author={Wei CHEN, Johan BAUWELINCK, Peter OSSIEUR, Xing-Zhi QIU, Jan VANDEWEGE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers},
year={2007},
volume={E90-C},
number={4},
pages={877-884},
abstract={This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below
keywords={},
doi={10.1093/ietele/e90-c.4.877},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers
T2 - IEICE TRANSACTIONS on Electronics
SP - 877
EP - 884
AU - Wei CHEN
AU - Johan BAUWELINCK
AU - Peter OSSIEUR
AU - Xing-Zhi QIU
AU - Jan VANDEWEGE
PY - 2007
DO - 10.1093/ietele/e90-c.4.877
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below
ER -
English
