It has been a main subject to reduce design time and cost not only in the field of digital LSI layout but also in the field of analog LSI, due to increasing LSI packing density and circuit complexity. Semicustom approaches are insufficient to design analog LSIs which require higher density chips and have many kinds of design specifications. As for custom approaches, a symbolic layout method is widely used, where an automatic compaction serves to shrink its chip size after placement and routing. However, most of analog LSIs are fabricated by bipolar process technology, which has many kinds of devices with various shaped patterns. And besides, there are many layout specifications, which are peculiar to analog LSIs and directly affect to circuit performance. So, it is necessary taking account of the layout specifications not only for placement and routing but also for compaction. This paper describes an approach for analog compaction. Given a layout pattern of placement and routing satisfying layout specifications, various techniques to take account of such specifications in a compaction method are discussed. This paper also proposes a clean-up function after compaction, which reduces detoured wire patterns and removes unnecessary vias. By the compaction with clean-up function, a final layout pattern becomes refined in quality.

We have introduced an extremely high resolution video system 'Super Hi-Vision' at the Kyushu National Museum. This feature opened in October 2005 with the purpose of exhibiting high-quality images of national treasures and traditional arts and crafts to its visitors. The system achieves high resolution using the spatial pixel offset method, quadrupling the horizontal and vertical resolution of HDTV. To display the images with high fidelity, it is important to manipulate the images on the basis of the system characteristics. This paper reports on the efforts to ensure image quality for this Super Hi-Vision System, focusing on resolution and color reproduction.

One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.

The main aim of device-level global routing is to obtain high-performance detailed routing under various layout constraints. This paper deals with global routing for analog function blocks. For analog LSIs, especially for those operating at high frequency, various layout constraints are specified prior to routing. Those constrainsts must be completely satisfied to achieve the required circuit performance. However, they are sometimes too hard to be solved by any heuristic method even if a problem is small in size. Thus, we propose a method based on the branch-and-bound algorithm, which can generate all possible solutions to find the best one. Unfortunately, the method tends to take a large amount of processing time. In order to defeat the drawbacks by accelerating the process, constraints are classified into two groups: constraints on single nets and constraints between two nets. Therefore our method consists of two parts: in the first part only constraints on single nets are processed and in the second part only constraints between two nets are processed. The method is efficient because many possible routes that violate layout constraints are rejected immediately in each part. This makes it possible to construct a smaller search tree and to reduce processing time. Additionally this idea, all nets processed in the second phase are sorted in the proper order to reduce the number of edges in the search tree. This saves much processing time, too. Experimental results show that our method can find a good global route for hard layout constraints in practical processing time, and also show that it is superior to the well-known simulated annealing method both in quality of solutions and in processing time.

This paper presents a novel regularity evaluation of placement structure and techniques for handling conditional design rules along with dynamic diffusion sharing and well island generation, which are developed based on Sequence-Pair. The regular structures such as topological rows, arrays and repetitive structures are characterized by the way of forming sub-sequences of a sequence-pair. A placement objective is formulated balancing the regularity and the area efficiency. Furthermore, diffusion sharing and well island can be also identified looking into forming of a sequence-pair. In experiments, we applied our regularity-oriented placement mixed with the constraint-driven technique to real analog designs, and attained the results comparable to manual designs even when imposing symmetry constraints. Besides, the results also revealed the regularity serves to increase row-structures applicable to the diffusion sharing for area saving and wire-length reduction.