IEICE TRANSACTIONS on transactions
Analog Layout Compaction with a Clean-up Function
Summary :
It has been a main subject to reduce design time and cost not only in the field of digital LSI layout but also in the field of analog LSI, due to increasing LSI packing density and circuit complexity. Semicustom approaches are insufficient to design analog LSIs which require higher density chips and have many kinds of design specifications. As for custom approaches, a symbolic layout method is widely used, where an automatic compaction serves to shrink its chip size after placement and routing. However, most of analog LSIs are fabricated by bipolar process technology, which has many kinds of devices with various shaped patterns. And besides, there are many layout specifications, which are peculiar to analog LSIs and directly affect to circuit performance. So, it is necessary taking account of the layout specifications not only for placement and routing but also for compaction. This paper describes an approach for analog compaction. Given a layout pattern of placement and routing satisfying layout specifications, various techniques to take account of such specifications in a compaction method are discussed. This paper also proposes a clean-up function after compaction, which reduces detoured wire patterns and removes unnecessary vias. By the compaction with clean-up function, a final layout pattern becomes refined in quality.
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- IEICE TRANSACTIONS on transactions Vol.E71-E No.12 pp.1243-1252
- Publication Date
- 1988/12/25
- Publicized
- Online ISSN
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- Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
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Masahiro KAWAKITA, Takahiro WATANABE, "Analog Layout Compaction with a Clean-up Function" in IEICE TRANSACTIONS on transactions,
vol. E71-E, no. 12, pp. 1243-1252, December 1988, doi: .
Abstract: It has been a main subject to reduce design time and cost not only in the field of digital LSI layout but also in the field of analog LSI, due to increasing LSI packing density and circuit complexity. Semicustom approaches are insufficient to design analog LSIs which require higher density chips and have many kinds of design specifications. As for custom approaches, a symbolic layout method is widely used, where an automatic compaction serves to shrink its chip size after placement and routing. However, most of analog LSIs are fabricated by bipolar process technology, which has many kinds of devices with various shaped patterns. And besides, there are many layout specifications, which are peculiar to analog LSIs and directly affect to circuit performance. So, it is necessary taking account of the layout specifications not only for placement and routing but also for compaction. This paper describes an approach for analog compaction. Given a layout pattern of placement and routing satisfying layout specifications, various techniques to take account of such specifications in a compaction method are discussed. This paper also proposes a clean-up function after compaction, which reduces detoured wire patterns and removes unnecessary vias. By the compaction with clean-up function, a final layout pattern becomes refined in quality.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e71-e_12_1243/_p
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@ARTICLE{e71-e_12_1243,
author={Masahiro KAWAKITA, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on transactions},
title={Analog Layout Compaction with a Clean-up Function},
year={1988},
volume={E71-E},
number={12},
pages={1243-1252},
abstract={It has been a main subject to reduce design time and cost not only in the field of digital LSI layout but also in the field of analog LSI, due to increasing LSI packing density and circuit complexity. Semicustom approaches are insufficient to design analog LSIs which require higher density chips and have many kinds of design specifications. As for custom approaches, a symbolic layout method is widely used, where an automatic compaction serves to shrink its chip size after placement and routing. However, most of analog LSIs are fabricated by bipolar process technology, which has many kinds of devices with various shaped patterns. And besides, there are many layout specifications, which are peculiar to analog LSIs and directly affect to circuit performance. So, it is necessary taking account of the layout specifications not only for placement and routing but also for compaction. This paper describes an approach for analog compaction. Given a layout pattern of placement and routing satisfying layout specifications, various techniques to take account of such specifications in a compaction method are discussed. This paper also proposes a clean-up function after compaction, which reduces detoured wire patterns and removes unnecessary vias. By the compaction with clean-up function, a final layout pattern becomes refined in quality.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Analog Layout Compaction with a Clean-up Function
T2 - IEICE TRANSACTIONS on transactions
SP - 1243
EP - 1252
AU - Masahiro KAWAKITA
AU - Takahiro WATANABE
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1988
AB - It has been a main subject to reduce design time and cost not only in the field of digital LSI layout but also in the field of analog LSI, due to increasing LSI packing density and circuit complexity. Semicustom approaches are insufficient to design analog LSIs which require higher density chips and have many kinds of design specifications. As for custom approaches, a symbolic layout method is widely used, where an automatic compaction serves to shrink its chip size after placement and routing. However, most of analog LSIs are fabricated by bipolar process technology, which has many kinds of devices with various shaped patterns. And besides, there are many layout specifications, which are peculiar to analog LSIs and directly affect to circuit performance. So, it is necessary taking account of the layout specifications not only for placement and routing but also for compaction. This paper describes an approach for analog compaction. Given a layout pattern of placement and routing satisfying layout specifications, various techniques to take account of such specifications in a compaction method are discussed. This paper also proposes a clean-up function after compaction, which reduces detoured wire patterns and removes unnecessary vias. By the compaction with clean-up function, a final layout pattern becomes refined in quality.
ER -
English
